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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-06-02 10:50:40 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-06-05 15:41:43 +0200 |
| commit | 7df8eea64a417f1db6777cddc1d7eda3634b7175 (patch) | |
| tree | f35a17cdb584cefe1e5d9615ff9ec67a87bc2d0e /drivers/clk/renesas | |
| parent | d0414e762f4d2151e29c1a89fafe0368d8362419 (diff) | |
| download | lwn-7df8eea64a417f1db6777cddc1d7eda3634b7175.tar.gz lwn-7df8eea64a417f1db6777cddc1d7eda3634b7175.zip | |
clk: renesas: rzg2l: Convert to readl_poll_timeout_atomic()
Use readl_poll_timeout_atomic() instead of open-coding the same
operation.
As typically no retries are needed, 10 µs is a suitable timeout value.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/900543d4b9abc1004e6aecdb676f23e5508ae96f.1685692810.git.geert+renesas@glider.be
Diffstat (limited to 'drivers/clk/renesas')
| -rw-r--r-- | drivers/clk/renesas/rzg2l-cpg.c | 16 |
1 files changed, 5 insertions, 11 deletions
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index ca8b921c7762..bc623515ad84 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -903,9 +903,9 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable) unsigned int reg = clock->off; struct device *dev = priv->dev; unsigned long flags; - unsigned int i; u32 bitmask = BIT(clock->bit); u32 value; + int error; if (!clock->off) { dev_dbg(dev, "%pC does not support ON/OFF\n", hw->clk); @@ -930,19 +930,13 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable) if (!priv->info->has_clk_mon_regs) return 0; - for (i = 1000; i > 0; --i) { - if (((readl(priv->base + CLK_MON_R(reg))) & bitmask)) - break; - cpu_relax(); - } - - if (!i) { + error = readl_poll_timeout_atomic(priv->base + CLK_MON_R(reg), value, + value & bitmask, 0, 10); + if (error) dev_err(dev, "Failed to enable CLK_ON %p\n", priv->base + CLK_ON_R(reg)); - return -ETIMEDOUT; - } - return 0; + return error; } static int rzg2l_mod_clock_enable(struct clk_hw *hw) |