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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2022-04-02 08:46:23 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-04-13 12:30:18 +0200 |
| commit | 6c185664b3d481292c41fbfe66ea19c84cb0237a (patch) | |
| tree | 7f0734e0e78d8e8793331c8fa56d1a18e9247a9a /drivers/clk/renesas/r9a07g043-cpg.c | |
| parent | c8b088224c25ef4f5270f9de6a3516181b63f38c (diff) | |
| download | lwn-6c185664b3d481292c41fbfe66ea19c84cb0237a.tar.gz lwn-6c185664b3d481292c41fbfe66ea19c84cb0237a.zip | |
clk: renesas: r9a07g043: Add GPIO clock and reset entries
Add GPIO clock and reset entries in CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220402074626.25624-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/r9a07g043-cpg.c')
| -rw-r--r-- | drivers/clk/renesas/r9a07g043-cpg.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index 81409ff37e2e..0c574e153d4d 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -112,6 +112,8 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 0x588, 0), DEF_MOD("sci1", R9A07G043_SCI1_CLKP, R9A07G043_CLK_P0, 0x588, 1), + DEF_MOD("gpio", R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK, + 0x598, 0), }; static struct rzg2l_reset r9a07g043_resets[] = { @@ -127,6 +129,9 @@ static struct rzg2l_reset r9a07g043_resets[] = { DEF_RST(R9A07G043_SCIF4_RST_SYSTEM_N, 0x884, 4), DEF_RST(R9A07G043_SCI0_RST, 0x888, 0), DEF_RST(R9A07G043_SCI1_RST, 0x888, 1), + DEF_RST(R9A07G043_GPIO_RSTN, 0x898, 0), + DEF_RST(R9A07G043_GPIO_PORT_RESETN, 0x898, 1), + DEF_RST(R9A07G043_GPIO_SPARE_RESETN, 0x898, 2), }; static const unsigned int r9a07g043_crit_mod_clks[] __initconst = { |