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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-03-10 11:36:33 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-03-21 11:12:23 +0100 |
| commit | 5f3a432a44b135db002d22446827cfa061fc0bfb (patch) | |
| tree | 0f3293a0bb16ac90e5319ca6b963d31d779594e7 /drivers/clk/renesas/r8a7795-cpg-mssr.c | |
| parent | c013fc7d23ca5b29f0cdc37d58b2466ead4fd5f6 (diff) | |
| download | lwn-5f3a432a44b135db002d22446827cfa061fc0bfb.tar.gz lwn-5f3a432a44b135db002d22446827cfa061fc0bfb.zip | |
clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init()
Pass the mode pin states from the SoC-specific CPG/MSSR driver to the
R-Car Gen3 CPG driver core, as their state will be needed to make some
core clock configuration decisions.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/r8a7795-cpg-mssr.c')
| -rw-r--r-- | drivers/clk/renesas/r8a7795-cpg-mssr.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index 608178618da8..4699f416e275 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -330,7 +330,7 @@ static int __init r8a7795_cpg_mssr_init(struct device *dev) return -EINVAL; } - return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR); + return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); } const struct cpg_mssr_info r8a7795_cpg_mssr_info __initconst = { |