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| author | Rajendra Nayak <rnayak@codeaurora.org> | 2016-09-29 14:05:45 +0530 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-11-01 18:39:17 -0700 |
| commit | 400d9fda39bc8e16412103796040aef484fe7f5d (patch) | |
| tree | bc99d5aba6b18334d9f8729766a4aef56ed92967 /drivers/clk/qcom/common.h | |
| parent | 31256f4892b443e1cf03de48ea447a86ec32038e (diff) | |
| download | lwn-400d9fda39bc8e16412103796040aef484fe7f5d.tar.gz lwn-400d9fda39bc8e16412103796040aef484fe7f5d.zip | |
clk: qcom: Enable FSM mode for votable alpha PLLs
The votable alpha PLLs need to have the fsm mode enabled as part
of the initialization. The sequence seems to be the same as used
by clk-pll, so move the function which does this into a common
place and reuse it for the clk-alpha-pll
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/qcom/common.h')
| -rw-r--r-- | drivers/clk/qcom/common.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h index ae9bdeb21f29..9fb5b8e89071 100644 --- a/drivers/clk/qcom/common.h +++ b/drivers/clk/qcom/common.h @@ -22,6 +22,13 @@ struct freq_tbl; struct clk_hw; struct parent_map; +#define PLL_LOCK_COUNT_SHIFT 8 +#define PLL_LOCK_COUNT_MASK 0x3f +#define PLL_BIAS_COUNT_SHIFT 14 +#define PLL_BIAS_COUNT_MASK 0x3f +#define PLL_VOTE_FSM_ENA BIT(20) +#define PLL_VOTE_FSM_RESET BIT(21) + struct qcom_cc_desc { const struct regmap_config *config; struct clk_regmap **clks; @@ -34,6 +41,8 @@ struct qcom_cc_desc { extern const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate); +extern void +qcom_pll_set_fsm_mode(struct regmap *m, u32 reg, u8 bias_count, u8 lock_count); extern int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map, u8 src); |