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| author | Runyang Chen <runyang.chen@mediatek.com> | 2023-05-25 15:50:11 +0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2023-06-12 18:24:38 -0700 |
| commit | 18eb864f1a2df1956a2829edd58d5d9e9e73bc19 (patch) | |
| tree | f78e65dac5a783598c0da39763d3bb6db7df9e07 /drivers/clk/mediatek | |
| parent | 2cf4ec53446fa5ab6f860b10a4d825311c40518d (diff) | |
| download | lwn-18eb864f1a2df1956a2829edd58d5d9e9e73bc19.tar.gz lwn-18eb864f1a2df1956a2829edd58d5d9e9e73bc19.zip | |
clk: mediatek: reset: add infra_ao reset support for MT8188
The infra_ao reset is needed for MT8188.
- Add mtk_clk_rst_desc for MT8188.
- Add register reset controller function for MT8188 infra_ao.
- Add infra_ao_idx_map for MT8188.
Signed-off-by: Runyang Chen <runyang.chen@mediatek.com>
Link: https://lore.kernel.org/r/20230525075011.7032-3-runyang.chen@mediatek.com
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek')
| -rw-r--r-- | drivers/clk/mediatek/clk-mt8188-infra_ao.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/drivers/clk/mediatek/clk-mt8188-infra_ao.c b/drivers/clk/mediatek/clk-mt8188-infra_ao.c index 91c35db40b4e..6d8764e05c8a 100644 --- a/drivers/clk/mediatek/clk-mt8188-infra_ao.c +++ b/drivers/clk/mediatek/clk-mt8188-infra_ao.c @@ -5,6 +5,7 @@ */ #include <dt-bindings/clock/mediatek,mt8188-clk.h> +#include <dt-bindings/reset/mt8188-resets.h> #include <linux/clk-provider.h> #include <linux/platform_device.h> @@ -176,9 +177,32 @@ static const struct mtk_gate infra_ao_clks[] = { "infra_ao_aes_msdcfde_0p", "top_aes_msdcfde", 18), }; +static u16 infra_ao_rst_ofs[] = { + INFRA_RST0_SET_OFFSET, + INFRA_RST1_SET_OFFSET, + INFRA_RST2_SET_OFFSET, + INFRA_RST3_SET_OFFSET, + INFRA_RST4_SET_OFFSET, +}; + +static u16 infra_ao_idx_map[] = { + [MT8188_INFRA_RST1_THERMAL_MCU_RST] = 1 * RST_NR_PER_BANK + 2, + [MT8188_INFRA_RST1_THERMAL_CTRL_RST] = 1 * RST_NR_PER_BANK + 4, + [MT8188_INFRA_RST3_PTP_CTRL_RST] = 3 * RST_NR_PER_BANK + 5, +}; + +static const struct mtk_clk_rst_desc infra_ao_rst_desc = { + .version = MTK_RST_SET_CLR, + .rst_bank_ofs = infra_ao_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs), + .rst_idx_map = infra_ao_idx_map, + .rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map), +}; + static const struct mtk_clk_desc infra_ao_desc = { .clks = infra_ao_clks, .num_clks = ARRAY_SIZE(infra_ao_clks), + .rst_desc = &infra_ao_rst_desc, }; static const struct of_device_id of_match_clk_mt8188_infra_ao[] = { |