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| author | Stephen Boyd <sboyd@kernel.org> | 2019-02-05 14:07:52 -0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2019-02-05 14:07:52 -0800 |
| commit | a49ba41c53d1da529e0573e08d5991abb72eaedf (patch) | |
| tree | be8f06d8817086217a331a4a356b1b753f1bd23b /drivers/clk/mediatek/clk-mt2712.c | |
| parent | bfeffd155283772bbe78c6a05dec7c0128ee500c (diff) | |
| parent | 491b00ff699356a8dab10eb517a1b44205514c9e (diff) | |
| download | lwn-a49ba41c53d1da529e0573e08d5991abb72eaedf.tar.gz lwn-a49ba41c53d1da529e0573e08d5991abb72eaedf.zip | |
Merge tag 'v5.1-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip
Pull Rockchip clk driver updates from Heiko Stuebner:
Fix for PLL rate calculation on rk3328 and SET_RATE_PARENT flag
for the display clock on rk3066.
* tag 'v5.1-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: add CLK_SET_RATE_PARENT for rk3066 lcdc dclks
clk: rockchip: fix frac settings of GPLL clock for rk3328
Diffstat (limited to 'drivers/clk/mediatek/clk-mt2712.c')
0 files changed, 0 insertions, 0 deletions