diff options
| author | Aidan MacDonald <aidanmacdonald.0x0@gmail.com> | 2022-10-26 20:43:42 +0100 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2022-10-27 11:59:05 -0700 |
| commit | c799a77720dd350fd742a99d80139514a0b4df4d (patch) | |
| tree | 1014708eb544874800f81c1a3208ae80efeff800 /drivers/clk/ingenic/cgu.c | |
| parent | d84bf9d6308e2606b60bb5b4577f8b9ac295cf0b (diff) | |
| download | lwn-c799a77720dd350fd742a99d80139514a0b4df4d.tar.gz lwn-c799a77720dd350fd742a99d80139514a0b4df4d.zip | |
clk: ingenic: Add .set_rate_hook() for PLL clocks
The set rate hook is called immediately after updating the clock
register but before the spinlock is released. This allows another
register to be updated alongside the main one, which is needed to
handle the I2S divider on some SoCs.
Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Link: https://lore.kernel.org/r/20221026194345.243007-4-aidanmacdonald.0x0@gmail.com
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/ingenic/cgu.c')
| -rw-r--r-- | drivers/clk/ingenic/cgu.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c index 75524c606a90..1f7ba30f5a1b 100644 --- a/drivers/clk/ingenic/cgu.c +++ b/drivers/clk/ingenic/cgu.c @@ -232,6 +232,9 @@ ingenic_pll_set_rate(struct clk_hw *hw, unsigned long req_rate, writel(ctl, cgu->base + pll_info->reg); + if (pll_info->set_rate_hook) + pll_info->set_rate_hook(pll_info, rate, parent_rate); + /* If the PLL is enabled, verify that it's stable */ if (pll_info->enable_bit >= 0 && (ctl & BIT(pll_info->enable_bit))) ret = ingenic_pll_check_stable(cgu, pll_info); |