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| author | Jiancheng Xue <xuejiancheng@hisilicon.com> | 2016-10-29 14:13:37 +0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-11-11 15:43:49 -0800 |
| commit | 707d33cb0b731472b7564d9fad8d45cbbd7fece3 (patch) | |
| tree | 763dca679d262fc8ec1a3222c0caac6500e92966 /drivers/clk/hisilicon/Makefile | |
| parent | 1001354ca34179f3db924eb66672442a173147dc (diff) | |
| download | lwn-707d33cb0b731472b7564d9fad8d45cbbd7fece3.tar.gz lwn-707d33cb0b731472b7564d9fad8d45cbbd7fece3.zip | |
clk: hisilicon: add CRG driver for Hi3798CV200 SoC
Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset
Generator) module generates clock and reset signals used
by other module blocks on SoC.
Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/hisilicon/Makefile')
| -rw-r--r-- | drivers/clk/hisilicon/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile index e169ec7da023..581989111215 100644 --- a/drivers/clk/hisilicon/Makefile +++ b/drivers/clk/hisilicon/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o +obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o obj-$(CONFIG_RESET_HISI) += reset.o obj-$(CONFIG_STUB_CLK_HI6220) += clk-hi6220-stub.o |