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author | Linus Torvalds <torvalds@linux-foundation.org> | 2015-08-31 17:26:48 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2015-08-31 17:26:48 -0700 |
commit | f36fc04e4cdda9e4c72ee504e7dc638f9a168863 (patch) | |
tree | 27ccf1037fba7b0deeb5bfdfb748bd9cc97c293d /drivers/clk/clk-si5351.c | |
parent | 26f8b7edc9eab56638274f5db90848a6df602081 (diff) | |
parent | ba30011577330b7e29ecb5916d89c6db9fbc5b3d (diff) | |
download | lwn-f36fc04e4cdda9e4c72ee504e7dc638f9a168863.tar.gz lwn-f36fc04e4cdda9e4c72ee504e7dc638f9a168863.zip |
Merge tag 'clk-for-linus-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Michael Turquette:
"The clk framework changes for 4.3 are mostly updates to existing
drivers and the addition of new clock drivers. Stephen Boyd has also
done a lot of subsystem-wide driver clean-ups (thanks!). There are
also fixes to the framework core and changes to better split clock
provider drivers from clock consumer drivers"
* tag 'clk-for-linus-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (227 commits)
clk: s5pv210: add missing call to samsung_clk_of_add_provider()
clk: pistachio: correct critical clock list
clk: pistachio: Fix PLL rate calculation in integer mode
clk: pistachio: Fix override of clk-pll settings from boot loader
clk: pistachio: Fix 32bit integer overflows
clk: tegra: Fix some static checker problems
clk: qcom: Fix MSM8916 prng clock enable bit
clk: Add missing header for 'bool' definition to clk-conf.h
drivers/clk: appropriate __init annotation for const data
clk: rockchip: register pll mux before pll itself
clk: add bindings for the Ux500 clocks
clk/ARM: move Ux500 PRCC bases to the device tree
clk: remove duplicated code with __clk_set_parent_after
clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)
clk: Constify clk_hw argument to provider APIs
clk: Hi6220: add stub clock driver
dt-bindings: clk: Hi6220: Document stub clock driver
dt-bindings: arm: Hi6220: add doc for SRAM controller
clk: atlas7: fix pll missed divide NR in fraction mode
clk: atlas7: fix bit field and its root clk for coresight_tpiu
...
Diffstat (limited to 'drivers/clk/clk-si5351.c')
-rw-r--r-- | drivers/clk/clk-si5351.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c index e39e1e680b3c..5596c0aac22f 100644 --- a/drivers/clk/clk-si5351.c +++ b/drivers/clk/clk-si5351.c @@ -18,7 +18,7 @@ #include <linux/module.h> #include <linux/kernel.h> -#include <linux/clkdev.h> +#include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/err.h> @@ -439,7 +439,7 @@ static unsigned long si5351_pll_recalc_rate(struct clk_hw *hw, dev_dbg(&hwdata->drvdata->client->dev, "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n", - __func__, __clk_get_name(hwdata->hw.clk), + __func__, clk_hw_get_name(hw), hwdata->params.p1, hwdata->params.p2, hwdata->params.p3, parent_rate, (unsigned long)rate); @@ -497,7 +497,7 @@ static long si5351_pll_round_rate(struct clk_hw *hw, unsigned long rate, dev_dbg(&hwdata->drvdata->client->dev, "%s - %s: a = %lu, b = %lu, c = %lu, parent_rate = %lu, rate = %lu\n", - __func__, __clk_get_name(hwdata->hw.clk), a, b, c, + __func__, clk_hw_get_name(hw), a, b, c, *parent_rate, rate); return rate; @@ -521,7 +521,7 @@ static int si5351_pll_set_rate(struct clk_hw *hw, unsigned long rate, dev_dbg(&hwdata->drvdata->client->dev, "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n", - __func__, __clk_get_name(hwdata->hw.clk), + __func__, clk_hw_get_name(hw), hwdata->params.p1, hwdata->params.p2, hwdata->params.p3, parent_rate, rate); @@ -632,7 +632,7 @@ static unsigned long si5351_msynth_recalc_rate(struct clk_hw *hw, dev_dbg(&hwdata->drvdata->client->dev, "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, m = %lu, parent_rate = %lu, rate = %lu\n", - __func__, __clk_get_name(hwdata->hw.clk), + __func__, clk_hw_get_name(hw), hwdata->params.p1, hwdata->params.p2, hwdata->params.p3, m, parent_rate, (unsigned long)rate); @@ -663,7 +663,7 @@ static long si5351_msynth_round_rate(struct clk_hw *hw, unsigned long rate, divby4 = 1; /* multisync can set pll */ - if (__clk_get_flags(hwdata->hw.clk) & CLK_SET_RATE_PARENT) { + if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { /* * find largest integer divider for max * vco frequency and given target rate @@ -745,7 +745,7 @@ static long si5351_msynth_round_rate(struct clk_hw *hw, unsigned long rate, dev_dbg(&hwdata->drvdata->client->dev, "%s - %s: a = %lu, b = %lu, c = %lu, divby4 = %d, parent_rate = %lu, rate = %lu\n", - __func__, __clk_get_name(hwdata->hw.clk), a, b, c, divby4, + __func__, clk_hw_get_name(hw), a, b, c, divby4, *parent_rate, rate); return rate; @@ -777,7 +777,7 @@ static int si5351_msynth_set_rate(struct clk_hw *hw, unsigned long rate, dev_dbg(&hwdata->drvdata->client->dev, "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, divby4 = %d, parent_rate = %lu, rate = %lu\n", - __func__, __clk_get_name(hwdata->hw.clk), + __func__, clk_hw_get_name(hw), hwdata->params.p1, hwdata->params.p2, hwdata->params.p3, divby4, parent_rate, rate); @@ -1013,7 +1013,7 @@ static long si5351_clkout_round_rate(struct clk_hw *hw, unsigned long rate, rate = SI5351_CLKOUT_MIN_FREQ; /* request frequency if multisync master */ - if (__clk_get_flags(hwdata->hw.clk) & CLK_SET_RATE_PARENT) { + if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { /* use r divider for frequencies below 1MHz */ rdiv = SI5351_OUTPUT_CLK_DIV_1; while (rate < SI5351_MULTISYNTH_MIN_FREQ && @@ -1042,7 +1042,7 @@ static long si5351_clkout_round_rate(struct clk_hw *hw, unsigned long rate, dev_dbg(&hwdata->drvdata->client->dev, "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n", - __func__, __clk_get_name(hwdata->hw.clk), (1 << rdiv), + __func__, clk_hw_get_name(hw), (1 << rdiv), *parent_rate, rate); return rate; @@ -1093,7 +1093,7 @@ static int si5351_clkout_set_rate(struct clk_hw *hw, unsigned long rate, dev_dbg(&hwdata->drvdata->client->dev, "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n", - __func__, __clk_get_name(hwdata->hw.clk), (1 << rdiv), + __func__, clk_hw_get_name(hw), (1 << rdiv), parent_rate, rate); return 0; |