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| author | Joel Stanley <joel@jms.id.au> | 2017-06-29 15:31:07 +0930 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-06-29 18:47:35 -0700 |
| commit | 785b62167d2fb9f2b98432627e503d3759a48de9 (patch) | |
| tree | 418a8a3d6de04437d7aaccf1754b2621d6091f74 /drivers/clk/clk-gemini.c | |
| parent | 2b286b09a048df80fd5f7dfc5057c2837679a1ab (diff) | |
| download | lwn-785b62167d2fb9f2b98432627e503d3759a48de9.tar.gz lwn-785b62167d2fb9f2b98432627e503d3759a48de9.zip | |
clk: gemini: Read status before using the value
The probe does a shift and mask of val without having read it from the hardware.
Fixes: 846423f96721 ("clk: Add Gemini SoC clock controller")
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/clk-gemini.c')
| -rw-r--r-- | drivers/clk/clk-gemini.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/clk-gemini.c b/drivers/clk/clk-gemini.c index b82db96ce0c7..c391a49aaaff 100644 --- a/drivers/clk/clk-gemini.c +++ b/drivers/clk/clk-gemini.c @@ -306,6 +306,7 @@ static int gemini_clk_probe(struct platform_device *pdev) gemini_clk_data->hws[GEMINI_CLK_RTC] = hw; /* CPU clock derived as a fixed ratio from the AHB clock */ + regmap_read(map, GEMINI_GLOBAL_STATUS, &val); val >>= CPU_AHB_RATIO_SHIFT; val &= CPU_AHB_RATIO_MASK; hw = clk_hw_register_fixed_factor(NULL, "cpu", "ahb", 0, |