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| author | Claudiu Beznea <claudiu.beznea@microchip.com> | 2023-06-15 12:32:24 +0300 |
|---|---|---|
| committer | Claudiu Beznea <claudiu.beznea@microchip.com> | 2023-06-21 10:42:48 +0300 |
| commit | a673dae8c4ad9ee02a80617c6569ac66991c6c82 (patch) | |
| tree | 9c3242fa35cf527ac2ab65d46a37d18589009ee3 /drivers/clk/at91/sama7g5.c | |
| parent | 077782e3f2f34003fb8d13f8becfeab69c4f6570 (diff) | |
| download | lwn-a673dae8c4ad9ee02a80617c6569ac66991c6c82.tar.gz lwn-a673dae8c4ad9ee02a80617c6569ac66991c6c82.zip | |
clk: at91: clk-sam9x60-pll: add support for parent_hw
Add support for parent_hw in SAM9X60 PLL clock drivers.
With this parent-child relation is described with pointers rather
than strings making registration a bit faster.
All the SoC based drivers that rely on clk-sam9x60-pll were adapted
to the new API change. The switch itself for SoCs will be done
in subsequent patches.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20230615093227.576102-9-claudiu.beznea@microchip.com
Diffstat (limited to 'drivers/clk/at91/sama7g5.c')
| -rw-r--r-- | drivers/clk/at91/sama7g5.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index 42f2f61cc6d1..3297e028c2c5 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -975,7 +975,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np) case PLL_TYPE_DIV: hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, sama7g5_plls[i][j].n, - sama7g5_plls[i][j].p, i, + sama7g5_plls[i][j].p, NULL, i, sama7g5_plls[i][j].c, sama7g5_plls[i][j].l, sama7g5_plls[i][j].f, |