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authorPaul Walmsley <paul.walmsley@sifive.com>2019-04-30 13:50:58 -0700
committerStephen Boyd <sboyd@kernel.org>2019-05-03 09:20:48 -0700
commit7b9487a9a5c41ce0ff4f6ca74652e99541bd51c3 (patch)
tree4020274afca1241fe429f4685a6b0439e0c9c251 /drivers/clk/Makefile
parenta6c6cb2e8bdf5abe53656c9d625fc3b7974432ff (diff)
downloadlwn-7b9487a9a5c41ce0ff4f6ca74652e99541bd51c3.tar.gz
lwn-7b9487a9a5c41ce0ff4f6ca74652e99541bd51c3.zip
clk: analogbits: add Wide-Range PLL library
Add common library code for the Analog Bits Wide-Range PLL (WRPLL) IP block, as implemented in TSMC CLN28HPC. There is no bus interface or register target associated with this PLL. This library is intended to be used by drivers for IP blocks that expose registers connected to the PLL configuration and status signals. Based on code originally written by Wesley Terpstra <wesley@sifive.com>: https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60 This version incorporates several changes requested by Stephen Boyd <sboyd@kernel.org>. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Wesley Terpstra <wesley@sifive.com> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Megan Wachs <megan@sifive.com> Cc: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org [sboyd@kernel.org: Fix some const issues] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/Makefile')
-rw-r--r--drivers/clk/Makefile1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 1db133652f0c..091ee1d8af65 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -64,6 +64,7 @@ obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
# please keep this section sorted lexicographically by directory path name
obj-y += actions/
+obj-y += analogbits/
obj-$(CONFIG_COMMON_CLK_AT91) += at91/
obj-$(CONFIG_ARCH_ARTPEC) += axis/
obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x/