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authorViresh Kumar <viresh.kumar@st.com>2012-04-10 09:02:35 +0530
committerArnd Bergmann <arnd@arndb.de>2012-05-12 21:19:23 +0200
commit55b8fd4f428501b0f35d62b8313311fd9863c188 (patch)
tree2c61fe9c307baa73048345adbb11e20e5eeb586e /drivers/clk/Makefile
parente12ff34402bd3a6cbeab0423012066874bb10f4b (diff)
downloadlwn-55b8fd4f428501b0f35d62b8313311fd9863c188.tar.gz
lwn-55b8fd4f428501b0f35d62b8313311fd9863c188.zip
SPEAr: clk: Add VCO-PLL Synthesizer clock
All SPEAr SoC's contain PLLs. Their Fout is derived based on following equations - In normal mode vco = (2 * M[15:8] * Fin)/N - In Dithered mode vco = (2 * M[15:0] * Fin)/(256 * N) pll_rate = vco/2^p vco and pll are very closely bound to each other, "vco needs to program: mode, m & n" and "pll needs to program p", both share common enable/disable logic and registers. This patch adds in support for this type of clock. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Reviewed-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/Makefile')
-rw-r--r--drivers/clk/Makefile3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 24aa7144811b..0f5e03d1ef5c 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -2,3 +2,6 @@
obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o
obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed-rate.o clk-gate.o \
clk-mux.o clk-divider.o clk-fixed-factor.o
+
+# SoCs specific
+obj-$(CONFIG_PLAT_SPEAR) += spear/