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| author | Alexandru Ardelean <alexandru.ardelean@analog.com> | 2021-02-01 17:12:42 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2021-02-08 18:13:12 -0800 |
| commit | 324a810583ffec3e5c6e7e35bc202904d362e71b (patch) | |
| tree | 9c509095b1b58009fd865b79d722edbb7e004233 /drivers/clk/Kconfig | |
| parent | 5c8fe583cce542aa0b84adc939ce85293de36e5e (diff) | |
| download | lwn-324a810583ffec3e5c6e7e35bc202904d362e71b.tar.gz lwn-324a810583ffec3e5c6e7e35bc202904d362e71b.zip | |
clk: axi-clkgen: replace ARCH dependencies with driver deps
The intent is to be able to run this driver to access the IP core in setups
where FPGA board is also connected via a PCIe bus. In such cases the number
of combinations explodes, where the host system can be an x86 with Xilinx
Zynq/ZynqMP/Microblaze board connected via PCIe.
Or even a ZynqMP board with a ZynqMP/Zynq/Microblaze connected via PCIe.
To accommodate for these cases, this change removes the limitation for this
driver to be compilable only on Zynq/Microblaze architectures.
And adds dependencies on the mechanisms required by the driver to work (OF
and HAS_IOMEM).
Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Link: https://lore.kernel.org/r/20210201151245.21845-2-alexandru.ardelean@analog.com
Acked-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Moritz Fischer <mdf@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/Kconfig')
| -rw-r--r-- | drivers/clk/Kconfig | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 85856cff506c..cee1d4e657bc 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -247,7 +247,8 @@ config CLK_TWL6040 config COMMON_CLK_AXI_CLKGEN tristate "AXI clkgen driver" - depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST + depends on HAS_IOMEM || COMPILE_TEST + depends on OF help Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx FPGAs. It is commonly used in Analog Devices' reference designs. |