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| author | Jeff Garzik <jeff@garzik.org> | 2009-04-07 19:18:32 -0400 |
|---|---|---|
| committer | Jeff Garzik <jgarzik@redhat.com> | 2009-09-01 19:47:19 -0400 |
| commit | 2fc37adba0fb05760b8635c6706773af828ccf3c (patch) | |
| tree | 821acd350a7e315481b0bf8f2478797dbb946588 /drivers/ata/sata_sil.c | |
| parent | 54c38444fad6a99b4b19512f8f0055d69115e69e (diff) | |
| download | lwn-2fc37adba0fb05760b8635c6706773af828ccf3c.tar.gz lwn-2fc37adba0fb05760b8635c6706773af828ccf3c.zip | |
[libata] sata_sil: disable DMA engine in sil_freeze()
We must disable the DMA engine before accessing taskfile registers.
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/ata/sata_sil.c')
| -rw-r--r-- | drivers/ata/sata_sil.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/ata/sata_sil.c b/drivers/ata/sata_sil.c index 35bd5cc7f285..3cb69d5fb817 100644 --- a/drivers/ata/sata_sil.c +++ b/drivers/ata/sata_sil.c @@ -565,6 +565,19 @@ static void sil_freeze(struct ata_port *ap) tmp |= SIL_MASK_IDE0_INT << ap->port_no; writel(tmp, mmio_base + SIL_SYSCFG); readl(mmio_base + SIL_SYSCFG); /* flush */ + + /* Ensure DMA_ENABLE is off. + * + * This is because the controller will not give us access to the + * taskfile registers while a DMA is in progress + */ + iowrite8(ioread8(ap->ioaddr.bmdma_addr) & ~SIL_DMA_ENABLE, + ap->ioaddr.bmdma_addr); + + /* According to ata_bmdma_stop, an HDMA transition requires + * on PIO cycle. But we can't read a taskfile register. + */ + ioread8(ap->ioaddr.bmdma_addr); } static void sil_thaw(struct ata_port *ap) |