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| author | Alan Cox <alan@lxorguk.ukuu.org.uk> | 2008-05-29 22:10:58 +0100 |
|---|---|---|
| committer | Jeff Garzik <jgarzik@redhat.com> | 2008-06-04 06:40:41 -0400 |
| commit | a57c1bade5a0ee5cd8b74502db9cbebb7f5780b2 (patch) | |
| tree | 7919f7e4d85d512442698819db2ef98ed9121574 /drivers/ata/pata_scc.c | |
| parent | 4f0ebe3cc57f18ba26317b56b80b108c2848b1de (diff) | |
| download | lwn-a57c1bade5a0ee5cd8b74502db9cbebb7f5780b2.tar.gz lwn-a57c1bade5a0ee5cd8b74502db9cbebb7f5780b2.zip | |
libata-sff: Fix oops reported in kerneloops.org for pnp devices with no ctl
- Make ata_sff_altstatus private so nobody uses it by mistake
- Drop the 400nS delay from it
Add
ata_sff_irq_status - encapsulates the IRQ check logic
This function keeps the existing behaviour for altstatus using devices. I
actually suspect the logic was wrong before the changes but -rc isn't the
time to play with that
ata_sff_sync - ensure writes hit the device
Really we want an io* operation for 'is posted' eg ioisposted(ioaddr) so
that we can fix the nasty delay this causes on most systems.
- ata_sff_pause - 400nS delay
Ensure the command hit the device and delay 400nS
- ata_sff_dma_pause
Ensure the I/O hit the device and enforce an HDMA1:0 transition delay.
Requires altstatus register exists, BUG if not so we don't risk
corruption in MWDMA modes. (UDMA the checksum will save your backside in
theory)
The only other complication then is devices with their own handlers.
rb532 can use dma_pause but scc needs to access its own altstatus
register for internal errata workarounds so directly call the drivers own
altstatus function.
Signed-off-by: Alan Cox <alan@redhat.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/ata/pata_scc.c')
| -rw-r--r-- | drivers/ata/pata_scc.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/ata/pata_scc.c b/drivers/ata/pata_scc.c index e965b251ca24..bbf5aa345e68 100644 --- a/drivers/ata/pata_scc.c +++ b/drivers/ata/pata_scc.c @@ -726,7 +726,7 @@ static void scc_bmdma_stop (struct ata_queued_cmd *qc) in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START); /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ - ata_sff_altstatus(ap); /* dummy read */ + ata_sff_dma_pause(ap); /* dummy read */ } /** @@ -747,7 +747,8 @@ static u8 scc_bmdma_status (struct ata_port *ap) return host_stat; /* errata A252,A308 workaround: Step4 */ - if ((ata_sff_altstatus(ap) & ATA_ERR) && (int_status & INTSTS_INTRQ)) + if ((scc_check_altstatus(ap) & ATA_ERR) + && (int_status & INTSTS_INTRQ)) return (host_stat | ATA_DMA_INTR); /* errata A308 workaround Step5 */ |