diff options
| author | Sergei Shtylyov <sshtylyov@ru.mvista.com> | 2009-12-07 23:25:52 +0400 |
|---|---|---|
| committer | Jeff Garzik <jgarzik@redhat.com> | 2010-03-01 14:58:42 -0500 |
| commit | 60661933995bc7a09686c901439e17c2a4ea7d5d (patch) | |
| tree | 3aed309842d39e19e4db700b4f0222fc3acbd2a8 /drivers/ata/pata_hpt3x2n.c | |
| parent | 56f46f8c8741d02516d9150a46a5b05fe910ee11 (diff) | |
| download | lwn-60661933995bc7a09686c901439e17c2a4ea7d5d.tar.gz lwn-60661933995bc7a09686c901439e17c2a4ea7d5d.zip | |
pata_hpt3x2n: always stretch UltraDMA timing
The UltraDMA Tss timing must be stretched with ATA clock of 66 MHz, but the
driver only does this when PCI clock is 66 MHz, whereas it always programs
DPLL clock (which is used as the ATA clock) to 66 MHz.
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: <stable@kernel.org>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/ata/pata_hpt3x2n.c')
| -rw-r--r-- | drivers/ata/pata_hpt3x2n.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/drivers/ata/pata_hpt3x2n.c b/drivers/ata/pata_hpt3x2n.c index dd26bc73bd9a..269b5dbe51bb 100644 --- a/drivers/ata/pata_hpt3x2n.c +++ b/drivers/ata/pata_hpt3x2n.c @@ -25,7 +25,7 @@ #include <linux/libata.h> #define DRV_NAME "pata_hpt3x2n" -#define DRV_VERSION "0.3.8" +#define DRV_VERSION "0.3.9" enum { HPT_PCI_FAST = (1 << 31), @@ -544,16 +544,16 @@ static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id) pci_mhz); /* Set our private data up. We only need a few flags so we use it directly */ - if (pci_mhz > 60) { + if (pci_mhz > 60) hpriv = (void *)(PCI66 | USE_DPLL); - /* - * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in - * the MISC. register to stretch the UltraDMA Tss timing. - * NOTE: This register is only writeable via I/O space. - */ - if (dev->device == PCI_DEVICE_ID_TTI_HPT371) - outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c); - } + + /* + * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in + * the MISC. register to stretch the UltraDMA Tss timing. + * NOTE: This register is only writeable via I/O space. + */ + if (dev->device == PCI_DEVICE_ID_TTI_HPT371) + outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c); /* Now kick off ATA set up */ return ata_pci_sff_init_one(dev, ppi, &hpt3x2n_sht, hpriv); |