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| author | Dan Williams <dan.j.williams@intel.com> | 2009-09-08 17:42:50 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2009-09-08 17:42:50 -0700 |
| commit | 0403e3827788d878163f9ef0541b748b0f88ca5d (patch) | |
| tree | 2dc73744bd92c268a1310f24668167f130877278 /crypto/async_tx/async_memset.c | |
| parent | f9dd2134374c8de6b911e2b8652c6c9622eaa658 (diff) | |
| download | lwn-0403e3827788d878163f9ef0541b748b0f88ca5d.tar.gz lwn-0403e3827788d878163f9ef0541b748b0f88ca5d.zip | |
dmaengine: add fence support
Some engines optimize operation by reading ahead in the descriptor chain
such that descriptor2 may start execution before descriptor1 completes.
If descriptor2 depends on the result from descriptor1 then a fence is
required (on descriptor2) to disable this optimization. The async_tx
api could implicitly identify dependencies via the 'depend_tx'
parameter, but that would constrain cases where the dependency chain
only specifies a completion order rather than a data dependency. So,
provide an ASYNC_TX_FENCE to explicitly identify data dependencies.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'crypto/async_tx/async_memset.c')
| -rw-r--r-- | crypto/async_tx/async_memset.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/crypto/async_tx/async_memset.c b/crypto/async_tx/async_memset.c index b896a6e5f673..a374784e3329 100644 --- a/crypto/async_tx/async_memset.c +++ b/crypto/async_tx/async_memset.c @@ -49,9 +49,12 @@ async_memset(struct page *dest, int val, unsigned int offset, size_t len, if (device) { dma_addr_t dma_dest; - unsigned long dma_prep_flags; + unsigned long dma_prep_flags = 0; - dma_prep_flags = submit->cb_fn ? DMA_PREP_INTERRUPT : 0; + if (submit->cb_fn) + dma_prep_flags |= DMA_PREP_INTERRUPT; + if (submit->flags & ASYNC_TX_FENCE) + dma_prep_flags |= DMA_PREP_FENCE; dma_dest = dma_map_page(device->dev, dest, offset, len, DMA_FROM_DEVICE); |