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| author | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2023-05-16 15:30:10 +0200 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2023-05-23 06:24:07 -0700 |
| commit | b8ae83eb0c9648a3f9c386cfb191e31139050143 (patch) | |
| tree | 4dd1b9e6823eb7f73e43b9d50e40e0a3d977ffbd /arch | |
| parent | b002bac7b4847aa11a6a56d14b2d75d4118f9591 (diff) | |
| download | lwn-b8ae83eb0c9648a3f9c386cfb191e31139050143.tar.gz lwn-b8ae83eb0c9648a3f9c386cfb191e31139050143.zip | |
arm64: dts: qcom: sm8550-qrd: add PCIe0
Add PCIe0 nodes used with WCN7851 device. The PCIe1 is not connected,
thus skip pcie_1_phy_aux_clk input clock to GCC.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230516133011.108093-1-krzysztof.kozlowski@linaro.org
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index d5a645ee2a61..88f27a632a4d 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -359,6 +359,38 @@ }; }; +&gcc { + clocks = <&bi_tcxo_div2>, <&sleep_clk>, + <&pcie0_phy>, + <&pcie1_phy>, + <0>, + <&ufs_mem_phy 0>, + <&ufs_mem_phy 1>, + <&ufs_mem_phy 2>, + <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; +}; + +&pcie_1_phy_aux_clk { + status = "disabled"; +}; + +&pcie0 { + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l1e_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; |