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authorLen Brown <len.brown@intel.com>2017-01-07 23:21:18 -0500
committerLen Brown <len.brown@intel.com>2017-03-01 00:13:03 -0500
commit40496c8ee73a5ca4fa581badf2247418980586b1 (patch)
treec21350653cc5de76f33902dd919460382e737447 /arch
parentf2642888476d7faefa9695bbebb2abbaeb3685d8 (diff)
downloadlwn-40496c8ee73a5ca4fa581badf2247418980586b1.tar.gz
lwn-40496c8ee73a5ca4fa581badf2247418980586b1.zip
x86: msr-index.h: Define MSR_PKG_CST_CONFIG_CONTROL
define MSR_PKG_CST_CONFIG_CONTROL (0xE2), which is the string used by Intel Documentation. We use this MSR in intel_idle and turbostat by a previous name, to be updated in the next patch. Cc: x86@kernel.org Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/x86/include/asm/msr-index.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 710273c617b8..975f23eefe14 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -47,6 +47,7 @@
#define MSR_PLATFORM_INFO 0x000000ce
#define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2
+#define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
#define NHM_C3_AUTO_DEMOTE (1UL << 25)
#define NHM_C1_AUTO_DEMOTE (1UL << 26)
#define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25)