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| author | Emanuel Czirai <icanrealizeum@gmail.com> | 2016-09-02 07:35:50 +0200 |
|---|---|---|
| committer | Sasha Levin <alexander.levin@verizon.com> | 2016-09-15 18:54:06 -0400 |
| commit | 7c17faccf5276b2a85dadb877d2abc3e73041213 (patch) | |
| tree | 532980787f150bd92bdb6d6a2de425f9ce843a06 /arch | |
| parent | 18ec3adc3d999b303bcf0e1cb907d7dbfb645677 (diff) | |
| download | lwn-7c17faccf5276b2a85dadb877d2abc3e73041213.tar.gz lwn-7c17faccf5276b2a85dadb877d2abc3e73041213.zip | |
x86/AMD: Apply erratum 665 on machines without a BIOS fix
[ Upstream commit d1992996753132e2dafe955cccb2fb0714d3cfc4 ]
AMD F12h machines have an erratum which can cause DIV/IDIV to behave
unpredictably. The workaround is to set MSRC001_1029[31] but sometimes
there is no BIOS update containing that workaround so let's do it
ourselves unconditionally. It is simple enough.
[ Borislav: Wrote commit message. ]
Signed-off-by: Emanuel Czirai <icanrealizeum@gmail.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Yaowu Xu <yaowu@google.com>
Cc: stable@vger.kernel.org
Link: http://lkml.kernel.org/r/20160902053550.18097-1-bp@alien8.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86/kernel/cpu/amd.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 813d29d00a17..a86afc3741dc 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -603,6 +603,17 @@ static void init_amd_gh(struct cpuinfo_x86 *c) set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH); } +#define MSR_AMD64_DE_CFG 0xC0011029 + +static void init_amd_ln(struct cpuinfo_x86 *c) +{ + /* + * Apply erratum 665 fix unconditionally so machines without a BIOS + * fix work. + */ + msr_set_bit(MSR_AMD64_DE_CFG, 31); +} + static void init_amd_bd(struct cpuinfo_x86 *c) { u64 value; @@ -672,6 +683,7 @@ static void init_amd(struct cpuinfo_x86 *c) case 6: init_amd_k7(c); break; case 0xf: init_amd_k8(c); break; case 0x10: init_amd_gh(c); break; + case 0x12: init_amd_ln(c); break; case 0x15: init_amd_bd(c); break; } |