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| author | Finn Thain <fthain@telegraphics.com.au> | 2014-01-13 00:56:38 +1100 |
|---|---|---|
| committer | Jiri Slaby <jslaby@suse.cz> | 2016-01-25 15:15:34 +0100 |
| commit | 6415eac837c3d1baa9f80d87bbad1e2fef0eab5a (patch) | |
| tree | 8a9f2c5687d8a30e0e6b7d27abd74a4a950e6392 /arch | |
| parent | fbe21cee2531ce936d26561f3a507823935514ab (diff) | |
| download | lwn-6415eac837c3d1baa9f80d87bbad1e2fef0eab5a.tar.gz lwn-6415eac837c3d1baa9f80d87bbad1e2fef0eab5a.zip | |
m68k/mac: Make SCC reset work more reliably
commit 56931d73697c99ecf7aba6ae86c94d3a2d15d596 upstream.
For SCC initialization we cannot assume that the control register is in
the correct state to accept a register pointer. So first read from the
control register in order to "sync" up.
Signed-off-by: Finn Thain <fthain@telegraphics.com.au>
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Oliver Neukum <ONeukum@suse.com>
Signed-off-by: Jiri Slaby <jslaby@suse.cz>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/m68k/kernel/head.S | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/m68k/kernel/head.S b/arch/m68k/kernel/head.S index ac85f16534af..4180f8b20374 100644 --- a/arch/m68k/kernel/head.S +++ b/arch/m68k/kernel/head.S @@ -2909,7 +2909,9 @@ func_start serial_init,%d0/%d1/%a0/%a1 #if defined(MAC_USE_SCC_A) || defined(MAC_USE_SCC_B) movel %pc@(L(mac_sccbase)),%a0 - /* Reset SCC device */ + /* Reset SCC register pointer */ + moveb %a0@(mac_scc_cha_a_ctrl_offset),%d0 + /* Reset SCC device: write register pointer then register value */ moveb #9,%a0@(mac_scc_cha_a_ctrl_offset) moveb #0xc0,%a0@(mac_scc_cha_a_ctrl_offset) /* Wait for 5 PCLK cycles, which is about 68 CPU cycles */ |