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| author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2013-09-27 08:37:59 +0200 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2013-09-30 09:58:44 -0700 |
| commit | bd737fea4e49b7c0e848e3765c6b45a858de41a8 (patch) | |
| tree | 6a42f57a8ee7217e5b0c1a5c3d48f890e77f2b8a /arch | |
| parent | 5abf58bf4cd0ab32b9737ea3d1cb6439ab646ad6 (diff) | |
| download | lwn-bd737fea4e49b7c0e848e3765c6b45a858de41a8.tar.gz lwn-bd737fea4e49b7c0e848e3765c6b45a858de41a8.zip | |
ARM: at91: sam9g45: shutdown ddr1 too when rebooting
Like we are doing on DDR0 we need to cleanly shutdown DDR1 if it is
used before rebooting.
If DDR1 is not initialized, we check it and avoid dereferencing its address.
Even by adding two more instructions, we are able to complete the procedure
within a single cache line.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-at91/at91sam9g45_reset.S | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mach-at91/at91sam9g45_reset.S b/arch/arm/mach-at91/at91sam9g45_reset.S index 721a1a34dd1d..c40c1e2ef80f 100644 --- a/arch/arm/mach-at91/at91sam9g45_reset.S +++ b/arch/arm/mach-at91/at91sam9g45_reset.S @@ -16,11 +16,17 @@ #include "at91_rstc.h" .arm +/* + * at91_ramc_base is an array void* + * init at NULL if only one DDR controler is present in or DT + */ .globl at91sam9g45_restart at91sam9g45_restart: ldr r5, =at91_ramc_base @ preload constants ldr r0, [r5] + ldr r5, [r5, #4] @ ddr1 + cmp r5, #0 ldr r4, =at91_rstc_base ldr r1, [r4] @@ -30,6 +36,8 @@ at91sam9g45_restart: .balign 32 @ align to cache line + strne r2, [r5, #AT91_DDRSDRC_RTR] @ disable DDR1 access + strne r3, [r5, #AT91_DDRSDRC_LPR] @ power down DDR1 str r2, [r0, #AT91_DDRSDRC_RTR] @ disable DDR0 access str r3, [r0, #AT91_DDRSDRC_LPR] @ power down DDR0 str r4, [r1, #AT91_RSTC_CR] @ reset processor |