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| author | Will Deacon <will.deacon@arm.com> | 2013-05-02 13:52:01 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2015-02-05 22:35:38 -0800 |
| commit | 716669313b88cce317a83230cde7644451aea9f4 (patch) | |
| tree | ce60f3e6dcf32aa6730f15d980a17aab4035d725 /arch | |
| parent | 98d1567891367f794f10b7cf907055abdb4f897b (diff) | |
| download | lwn-716669313b88cce317a83230cde7644451aea9f4.tar.gz lwn-716669313b88cce317a83230cde7644451aea9f4.zip | |
ARM: lpae: fix definition of PTE_HWTABLE_PTRS
commit e38a517578d6c0f764b0d0f6e26dcdf9f70c69d7 upstream.
For 2-level page tables, PTE_HWTABLE_PTRS describes the offset between
Linux PTEs and hardware PTEs. On LPAE, there is no distinction (since
we have 64-bit descriptors with plenty of space) so PTE_HWTABLE_PTRS
should be 0. Unfortunately, it is wrongly defined as PTRS_PER_PTE,
meaning that current pte table flushing is off by a page. Luckily,
all current LPAE implementations are SMP, so the hardware walker can
snoop L1.
This patch fixes the broken definition.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Cc: Hou Pengyang <houpengyang@huawei.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/include/asm/pgtable-3level.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h index 944551271e37..6d7c532c0c8a 100644 --- a/arch/arm/include/asm/pgtable-3level.h +++ b/arch/arm/include/asm/pgtable-3level.h @@ -33,7 +33,7 @@ #define PTRS_PER_PMD 512 #define PTRS_PER_PGD 4 -#define PTE_HWTABLE_PTRS (PTRS_PER_PTE) +#define PTE_HWTABLE_PTRS (0) #define PTE_HWTABLE_OFF (0) #define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u64)) |