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| author | Srinivas Kandagatla <srinivas.kandagatla@linaro.org> | 2017-09-18 12:04:37 +0200 |
|---|---|---|
| committer | Andy Gross <andy.gross@linaro.org> | 2017-10-11 15:52:34 -0500 |
| commit | fb83f201433d8e15ade29dbe6d8d43c810fa0b27 (patch) | |
| tree | e2919e6db885286297455402f5b33bfbcab68906 /arch | |
| parent | 3191b5b332f8982581d6bd5ae409590342d770ad (diff) | |
| download | lwn-fb83f201433d8e15ade29dbe6d8d43c810fa0b27.tar.gz lwn-fb83f201433d8e15ade29dbe6d8d43c810fa0b27.zip | |
ARM: dts: qcom-apq8064: disable gsbi6 i2c by default at soc dtsi
This patch marks gsbi i2c node at soc level dtsi, so that kernel
would not assume that its enabled and result in pin conflicts on
some boards like IFC6410 which do use these pins for uart.
Without this patch we see below pin conflict:
apq8064-pinctrl 800000.pinctrl: pin GPIO_16 already requested by
16540000.serial; cannot claim for 16580000.i2c
apq8064-pinctrl 800000.pinctrl: pin-16 (16580000.i2c) status -22
apq8064-pinctrl 800000.pinctrl: could not request pin 16 (GPIO_16)
from group gpio16 on device 800000.pinctrl
i2c_qup 16580000.i2c: Error applying setting, reverse things back
i2c_qup: probe of 16580000.i2c failed with error -22
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/qcom-apq8064.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index d08f3dbdb0c8..ed6d6b323cd9 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -590,6 +590,7 @@ clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; clock-names = "core", "iface"; + status = "disabled"; }; }; |