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| author | Juergen Gross <jgross@suse.com> | 2024-10-04 12:22:12 +0200 |
|---|---|---|
| committer | Juergen Gross <jgross@suse.com> | 2024-10-08 16:18:57 +0200 |
| commit | bf56c410162dbf2e27906acbdcd904cbbfdba302 (patch) | |
| tree | 9388d9cc479a54ebd30fb26fdf8d959b5897e1b8 /arch | |
| parent | 9af48210ea5f1539e1999154b0acd343efdb370b (diff) | |
| download | lwn-bf56c410162dbf2e27906acbdcd904cbbfdba302.tar.gz lwn-bf56c410162dbf2e27906acbdcd904cbbfdba302.zip | |
x86/xen: mark boot CPU of PV guest in MSR_IA32_APICBASE
Recent topology checks of the x86 boot code uncovered the need for
PV guests to have the boot cpu marked in the APICBASE MSR.
Fixes: 9d22c96316ac ("x86/topology: Handle bogus ACPI tables correctly")
Reported-by: Niels Dettenbach <nd@syndicat.com>
Signed-off-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Juergen Gross <jgross@suse.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86/xen/enlighten_pv.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index 2c12ae42dc8b..d6818c6cafda 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -1032,6 +1032,10 @@ static u64 xen_do_read_msr(unsigned int msr, int *err) switch (msr) { case MSR_IA32_APICBASE: val &= ~X2APIC_ENABLE; + if (smp_processor_id() == 0) + val |= MSR_IA32_APICBASE_BSP; + else + val &= ~MSR_IA32_APICBASE_BSP; break; } return val; |