diff options
| author | Olof Johansson <olof@lixom.net> | 2019-12-06 08:27:32 -0800 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2019-12-06 08:27:34 -0800 |
| commit | f7a1a1db9877799e15aba047acd799c2df811f88 (patch) | |
| tree | e70fc561521a9947627e4a530a0459d73eec8999 /arch | |
| parent | e89d108da909a4a248ab27cddd68eebaed2850f3 (diff) | |
| parent | 716864586c6261b079a4d5ebc02f19adc8e6aa38 (diff) | |
| download | lwn-f7a1a1db9877799e15aba047acd799c2df811f88.tar.gz lwn-f7a1a1db9877799e15aba047acd799c2df811f88.zip | |
Merge tag 'socfpga_update_for_v5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/fixes
SoCFPGA updates for v5.5
- Issue COLD reboot by default for SoCFPGA platforms
* tag 'socfpga_update_for_v5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
arm: socfpga: execute cold reboot by default
Link: https://lore.kernel.org/r/20191122182106.822-1-dinguyen@kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-socfpga/socfpga.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index 47ebcc8a5085..9e4cb2ffd580 100644 --- a/arch/arm/mach-socfpga/socfpga.c +++ b/arch/arm/mach-socfpga/socfpga.c @@ -73,10 +73,10 @@ static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd) temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL); - if (mode == REBOOT_HARD) - temp |= RSTMGR_CTRL_SWCOLDRSTREQ; - else + if (mode == REBOOT_WARM) temp |= RSTMGR_CTRL_SWWARMRSTREQ; + else + temp |= RSTMGR_CTRL_SWCOLDRSTREQ; writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL); } @@ -86,10 +86,10 @@ static void socfpga_arria10_restart(enum reboot_mode mode, const char *cmd) temp = readl(rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL); - if (mode == REBOOT_HARD) - temp |= RSTMGR_CTRL_SWCOLDRSTREQ; - else + if (mode == REBOOT_WARM) temp |= RSTMGR_CTRL_SWWARMRSTREQ; + else + temp |= RSTMGR_CTRL_SWCOLDRSTREQ; writel(temp, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL); } |