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| author | Sean Christopherson <sean.j.christopherson@intel.com> | 2020-03-02 18:02:36 -0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2020-03-16 17:57:44 +0100 |
| commit | bb1fcc70d98f040e3cc469b079d3f38fc541cb95 (patch) | |
| tree | 318393d7e8b0fda9862851dc9207f6c89def3b75 /arch/x86/kvm/mmu/paging_tmpl.h | |
| parent | 8053f924cad30bf9f9a24e02b6c8ddfabf5202ea (diff) | |
| download | lwn-bb1fcc70d98f040e3cc469b079d3f38fc541cb95.tar.gz lwn-bb1fcc70d98f040e3cc469b079d3f38fc541cb95.zip | |
KVM: nVMX: Allow L1 to use 5-level page walks for nested EPT
Add support for 5-level nested EPT, and advertise said support in the
EPT capabilities MSR. KVM's MMU can already handle 5-level legacy page
tables, there's no reason to force an L1 VMM to use shadow paging if it
wants to employ 5-level page tables.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'arch/x86/kvm/mmu/paging_tmpl.h')
| -rw-r--r-- | arch/x86/kvm/mmu/paging_tmpl.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/kvm/mmu/paging_tmpl.h b/arch/x86/kvm/mmu/paging_tmpl.h index e4c8a4cbf407..6b15b58f3ecc 100644 --- a/arch/x86/kvm/mmu/paging_tmpl.h +++ b/arch/x86/kvm/mmu/paging_tmpl.h @@ -66,7 +66,7 @@ #define PT_GUEST_ACCESSED_SHIFT 8 #define PT_HAVE_ACCESSED_DIRTY(mmu) ((mmu)->ept_ad) #define CMPXCHG cmpxchg64 - #define PT_MAX_FULL_LEVELS 4 + #define PT_MAX_FULL_LEVELS PT64_ROOT_MAX_LEVEL #else #error Invalid PTTYPE value #endif |