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| author | Robert Richter <robert.richter@amd.com> | 2011-05-30 16:31:11 +0200 |
|---|---|---|
| committer | Robert Richter <robert.richter@amd.com> | 2011-05-30 16:36:54 +0200 |
| commit | cbf74cea070fa1f705de4712e25d9e56ae6543c7 (patch) | |
| tree | dce39e94a735df4953415720d85d7ed106f71075 /arch/x86/kernel | |
| parent | b76a06e08d94b2a63e47837dfe46bbbf0a3af6c2 (diff) | |
| download | lwn-cbf74cea070fa1f705de4712e25d9e56ae6543c7.tar.gz lwn-cbf74cea070fa1f705de4712e25d9e56ae6543c7.zip | |
oprofile, x86: Add comments to IBS LVT offset initialization
Adding a comment in the code as IBS LVT setup is not obvious at all ...
Signed-off-by: Robert Richter <robert.richter@amd.com>
Diffstat (limited to 'arch/x86/kernel')
| -rw-r--r-- | arch/x86/kernel/apic/apic.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index fabf01eff771..a0bf78a0918c 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -390,7 +390,8 @@ static unsigned int reserve_eilvt_offset(int offset, unsigned int new) /* * If mask=1, the LVT entry does not generate interrupts while mask=0 - * enables the vector. See also the BKDGs. + * enables the vector. See also the BKDGs. Must be called with + * preemption disabled. */ int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) |