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| author | Peter Zijlstra <a.p.zijlstra@chello.nl> | 2012-06-08 14:50:50 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2012-07-05 21:55:57 +0200 |
| commit | c93dc84cbe32435be3ffa2fbde355eff94955c32 (patch) | |
| tree | b650cfcea486aa0dd1612f187156c7b84fb97661 /arch/x86/kernel/cpu/perf_event.h | |
| parent | f285f92f7e4c9af20149130c8fd5027131b39b0e (diff) | |
| download | lwn-c93dc84cbe32435be3ffa2fbde355eff94955c32.tar.gz lwn-c93dc84cbe32435be3ffa2fbde355eff94955c32.zip | |
perf/x86: Add a microcode revision check for SNB-PEBS
Recent Intel microcode resolved the SNB-PEBS issues, so conditionally
enable PEBS on SNB hardware depending on the microcode revision.
Thanks to Stephane for figuring out the various microcode revisions.
Suggested-by: Stephane Eranian <eranian@google.com>
Acked-by: Borislav Petkov <borislav.petkov@amd.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/n/tip-v3672ziwh9damwqwh1uz3krm@git.kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86/kernel/cpu/perf_event.h')
| -rw-r--r-- | arch/x86/kernel/cpu/perf_event.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h index 83238f2a12b2..3f5c66904355 100644 --- a/arch/x86/kernel/cpu/perf_event.h +++ b/arch/x86/kernel/cpu/perf_event.h @@ -361,6 +361,8 @@ struct x86_pmu { void (*cpu_starting)(int cpu); void (*cpu_dying)(int cpu); void (*cpu_dead)(int cpu); + + void (*check_microcode)(void); void (*flush_branch_stack)(void); /* @@ -373,7 +375,7 @@ struct x86_pmu { * Intel DebugStore bits */ int bts, pebs; - int bts_active, pebs_active; + int bts_active, pebs_active, pebs_broken; int pebs_record_size; void (*drain_pebs)(struct pt_regs *regs); struct event_constraint *pebs_constraints; |