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| author | Kirill A. Shutemov <kirill.shutemov@linux.intel.com> | 2017-07-17 01:59:54 +0300 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2017-07-21 10:05:19 +0200 |
| commit | 77ef56e4f0fbb350d93289aa025c7d605af012d4 (patch) | |
| tree | 74562d80774df19f6be3a40304b0e77d65d6f9b4 /arch/x86/Kconfig | |
| parent | ee00f4a32a76ef631394f31d5b6028d50462b357 (diff) | |
| download | lwn-77ef56e4f0fbb350d93289aa025c7d605af012d4.tar.gz lwn-77ef56e4f0fbb350d93289aa025c7d605af012d4.zip | |
x86: Enable 5-level paging support via CONFIG_X86_5LEVEL=y
Most of things are in place and we can enable support for 5-level paging.
The patch makes XEN_PV and XEN_PVH dependent on !X86_5LEVEL. Both are
not ready to work with 5-level paging.
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Reviewed-by: Juergen Gross <jgross@suse.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Dave Hansen <dave.hansen@intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-arch@vger.kernel.org
Cc: linux-mm@kvack.org
Link: http://lkml.kernel.org/r/20170716225954.74185-9-kirill.shutemov@linux.intel.com
[ Minor readability edits. ]
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86/Kconfig')
| -rw-r--r-- | arch/x86/Kconfig | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 8328bcb9ce8b..ff637dedfafa 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -326,6 +326,7 @@ config FIX_EARLYCON_MEM config PGTABLE_LEVELS int + default 5 if X86_5LEVEL default 4 if X86_64 default 3 if X86_PAE default 2 @@ -1398,6 +1399,24 @@ config X86_PAE has the cost of more pagetable lookup overhead, and also consumes more pagetable space per process. +config X86_5LEVEL + bool "Enable 5-level page tables support" + depends on X86_64 + ---help--- + 5-level paging enables access to larger address space: + upto 128 PiB of virtual address space and 4 PiB of + physical address space. + + It will be supported by future Intel CPUs. + + Note: a kernel with this option enabled can only be booted + on machines that support the feature. + + See Documentation/x86/x86_64/5level-paging.txt for more + information. + + Say N if unsure. + config ARCH_PHYS_ADDR_T_64BIT def_bool y depends on X86_64 || X86_PAE |