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| author | Andi Kleen <andi@firstfloor.org> | 2009-02-12 13:49:31 +0100 |
|---|---|---|
| committer | H. Peter Anvin <hpa@zytor.com> | 2009-02-24 13:24:42 -0800 |
| commit | b276268631af3a1b0df871e10d19d492f0513d4b (patch) | |
| tree | 7646ccd6eb4987b02dcc777150d120b99069f8e0 /arch/x86/Kconfig | |
| parent | 41fdff322e26c4a86fe65cf577f2556a650cb7bc (diff) | |
| download | lwn-b276268631af3a1b0df871e10d19d492f0513d4b.tar.gz lwn-b276268631af3a1b0df871e10d19d492f0513d4b.zip | |
x86, mce, cmci: factor out threshold interrupt handler
Impact: cleanup; preparation for feature
The mce_amd_64 code has an own private MC threshold vector with an own
interrupt handler. Since Intel needs a similar handler
it makes sense to share the vector because both can not
be active at the same time.
I factored the common APIC handler code into a separate file which can
be used by both the Intel or AMD MC code.
This is needed for the next patch which adds an Intel specific
CMCI handler.
This patch should be a nop for AMD, it just moves some code
around.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch/x86/Kconfig')
| -rw-r--r-- | arch/x86/Kconfig | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 9c39095b33fc..52d7013785fe 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -751,6 +751,11 @@ config X86_MCE_AMD Additional support for AMD specific MCE features such as the DRAM Error Threshold. +config X86_MCE_THRESHOLD + depends on X86_MCE_AMD || X86_MCE_INTEL + bool + default y + config X86_MCE_NONFATAL tristate "Check for non-fatal errors on AMD Athlon/Duron / Intel Pentium 4" depends on X86_32 && X86_MCE |