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| author | David S. Miller <davem@davemloft.net> | 2014-09-26 21:58:33 -0700 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2014-10-05 16:53:39 -0700 |
| commit | 4397bed080598001e88f612deb8b080bb1cc2322 (patch) | |
| tree | c649278e09119997cb28176bb5b090b8b881fc5c /arch/sparc/mm/init_64.c | |
| parent | ac55c768143aa34cc3789c4820cbb0809a76fd9c (diff) | |
| download | lwn-4397bed080598001e88f612deb8b080bb1cc2322.tar.gz lwn-4397bed080598001e88f612deb8b080bb1cc2322.zip | |
sparc64: Define VA hole at run time, rather than at compile time.
Now that we use 4-level page tables, we can provide up to 53-bits of
virtual address space to the user.
Adjust the VA hole based upon the capabilities of the cpu type probed.
Signed-off-by: David S. Miller <davem@davemloft.net>
Acked-by: Bob Picco <bob.picco@oracle.com>
Diffstat (limited to 'arch/sparc/mm/init_64.c')
| -rw-r--r-- | arch/sparc/mm/init_64.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c index 091f846e6192..c241c5723373 100644 --- a/arch/sparc/mm/init_64.c +++ b/arch/sparc/mm/init_64.c @@ -1630,25 +1630,46 @@ static void __init page_offset_shift_patch(unsigned long phys_bits) } } +unsigned long sparc64_va_hole_top = 0xfffff80000000000UL; +unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL; + static void __init setup_page_offset(void) { unsigned long max_phys_bits = 40; if (tlb_type == cheetah || tlb_type == cheetah_plus) { + /* Cheetah/Panther support a full 64-bit virtual + * address, so we can use all that our page tables + * support. + */ + sparc64_va_hole_top = 0xfff0000000000000UL; + sparc64_va_hole_bottom = 0x0010000000000000UL; + max_phys_bits = 42; } else if (tlb_type == hypervisor) { switch (sun4v_chip_type) { case SUN4V_CHIP_NIAGARA1: case SUN4V_CHIP_NIAGARA2: + /* T1 and T2 support 48-bit virtual addresses. */ + sparc64_va_hole_top = 0xffff800000000000UL; + sparc64_va_hole_bottom = 0x0000800000000000UL; + max_phys_bits = 39; break; case SUN4V_CHIP_NIAGARA3: + /* T3 supports 48-bit virtual addresses. */ + sparc64_va_hole_top = 0xffff800000000000UL; + sparc64_va_hole_bottom = 0x0000800000000000UL; + max_phys_bits = 43; break; case SUN4V_CHIP_NIAGARA4: case SUN4V_CHIP_NIAGARA5: case SUN4V_CHIP_SPARC64X: default: + /* T4 and later support 52-bit virtual addresses. */ + sparc64_va_hole_top = 0xfff8000000000000UL; + sparc64_va_hole_bottom = 0x0008000000000000UL; max_phys_bits = 47; break; } |