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| author | Samuel Holland <samuel.holland@sifive.com> | 2024-03-26 21:49:46 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2024-04-29 10:49:28 -0700 |
| commit | 9546f00410ed88b8117388cfd74ea59f4616a158 (patch) | |
| tree | 1c0d8fc79fd666a1caf2c7a501ffef7d16a6354d /arch/riscv/mm/tlbflush.c | |
| parent | 038ac18aae935c89c874649acde5a82f588a12b4 (diff) | |
| download | lwn-9546f00410ed88b8117388cfd74ea59f4616a158.tar.gz lwn-9546f00410ed88b8117388cfd74ea59f4616a158.zip | |
riscv: Only send remote fences when some other CPU is online
If no other CPU is online, a local cache or TLB flush is sufficient.
These checks can be constant-folded when SMP is disabled.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/r/20240327045035.368512-6-samuel.holland@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/mm/tlbflush.c')
| -rw-r--r-- | arch/riscv/mm/tlbflush.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index da821315d43e..0901aa47b58f 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -79,7 +79,9 @@ static void __ipi_flush_tlb_all(void *info) void flush_tlb_all(void) { - if (riscv_use_sbi_for_rfence()) + if (num_online_cpus() < 2) + local_flush_tlb_all(); + else if (riscv_use_sbi_for_rfence()) sbi_remote_sfence_vma_asid(NULL, 0, FLUSH_TLB_MAX_SIZE, FLUSH_TLB_NO_ASID); else on_each_cpu(__ipi_flush_tlb_all, NULL, 1); |