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| author | Anup Patel <apatel@ventanamicro.com> | 2023-06-15 13:03:44 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2023-06-18 21:24:33 +0530 |
| commit | 77cf33c17154b7f8151429f6ba32049afc49f9c3 (patch) | |
| tree | 2b649f96f432bc4513c4667618b414f67af88f02 /arch/riscv/kvm/vcpu.c | |
| parent | 95c99104cb42bea5a0874c362f284ae4b91289dd (diff) | |
| download | lwn-77cf33c17154b7f8151429f6ba32049afc49f9c3.tar.gz lwn-77cf33c17154b7f8151429f6ba32049afc49f9c3.zip | |
RISC-V: KVM: Implement guest external interrupt line management
The RISC-V host will have one guest external interrupt line for each
VS-level IMSICs associated with a HART. The guest external interrupt
lines are per-HART resources and hypervisor can use HGEIE, HGEIP, and
HIE CSRs to manage these guest external interrupt lines.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv/kvm/vcpu.c')
| -rw-r--r-- | arch/riscv/kvm/vcpu.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 8bd9f2a8a0b9..2db62c6c0d3e 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -250,10 +250,12 @@ int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) { + kvm_riscv_aia_wakeon_hgei(vcpu, true); } void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) { + kvm_riscv_aia_wakeon_hgei(vcpu, false); } int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |