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| author | Atish Patra <atish.patra@wdc.com> | 2020-03-17 18:11:42 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2020-03-31 11:26:05 -0700 |
| commit | db5a79460315bd12dedee5f964cd72f3a534ecb2 (patch) | |
| tree | 09e805f9185e0653c4d7d11b7b8046223e933e4b /arch/riscv/kernel | |
| parent | f90b43ce176c129a84237c9d57fae51aeff3e6ec (diff) | |
| download | lwn-db5a79460315bd12dedee5f964cd72f3a534ecb2.tar.gz lwn-db5a79460315bd12dedee5f964cd72f3a534ecb2.zip | |
RISC-V: Add SBI HSM extension definitions
SBI specification defines HSM extension that allows to start/stop a hart
by a supervisor anytime. The specification is available at
https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc
Add those definitions here.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'arch/riscv/kernel')
0 files changed, 0 insertions, 0 deletions