diff options
| author | Anup Patel <Anup.Patel@wdc.com> | 2019-04-25 08:38:41 +0000 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-05-16 20:42:11 -0700 |
| commit | a3182c91ef4e7dda90ff080a4132efd3ecb8786a (patch) | |
| tree | 5309b2480f3c6bb9e6df4d7921c7a71ce18dcc4d /arch/riscv/kernel/traps.c | |
| parent | 6dcaf00487ca10d87e53fc8decb2e30f113c955d (diff) | |
| download | lwn-a3182c91ef4e7dda90ff080a4132efd3ecb8786a.tar.gz lwn-a3182c91ef4e7dda90ff080a4132efd3ecb8786a.zip | |
RISC-V: Access CSRs using CSR numbers
We should prefer accessing CSRs using their CSR numbers because:
1. It compiles fine with older toolchains.
2. We can use latest CSR names in #define macro names of CSR numbers
as-per RISC-V spec.
3. We can access newly added CSRs even if toolchain does not recognize
newly addes CSRs by name.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'arch/riscv/kernel/traps.c')
| -rw-r--r-- | arch/riscv/kernel/traps.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 86731a2fa218..cc9405420c70 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -159,9 +159,9 @@ void __init trap_init(void) * Set sup0 scratch register to 0, indicating to exception vector * that we are presently executing in the kernel */ - csr_write(sscratch, 0); + csr_write(CSR_SSCRATCH, 0); /* Set the exception vector address */ - csr_write(stvec, &handle_exception); + csr_write(CSR_STVEC, &handle_exception); /* Enable all interrupts */ - csr_write(sie, -1); + csr_write(CSR_SIE, -1); } |