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| author | Atish Patra <atishp@rivosinc.com> | 2022-07-22 09:50:45 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2022-08-11 14:36:13 -0700 |
| commit | 464b0187ff94fcc629fe7cd350e16a3b9e80ed9e (patch) | |
| tree | 56b5a4be274df53a837dc3377d94cd21e30606c5 /arch/riscv/include | |
| parent | bf952a290f7a9d818204b9b68e861655f8b15a65 (diff) | |
| download | lwn-464b0187ff94fcc629fe7cd350e16a3b9e80ed9e.tar.gz lwn-464b0187ff94fcc629fe7cd350e16a3b9e80ed9e.zip | |
RISC-V: Enable sstc extension parsing from DT
The ISA extension framework now allows parsing any multi-letter
ISA extension.
Enable that for sstc extension.
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20220722165047.519994-3-atishp@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/include')
| -rw-r--r-- | arch/riscv/include/asm/hwcap.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 4e2486881840..b186fff75198 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -53,6 +53,7 @@ extern unsigned long elf_hwcap; enum riscv_isa_ext_id { RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, RISCV_ISA_EXT_SVPBMT, + RISCV_ISA_EXT_SSTC, RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, }; |