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authorAnup Patel <apatel@ventanamicro.com>2022-07-22 18:54:54 +0530
committerAnup Patel <anup@brainfault.org>2023-10-20 16:50:28 +0530
commitdadf7886993c69c6838107573e250a3b3fda25e3 (patch)
treebed3be7976cd1bf40d6639eaef62addebe1947be /arch/riscv/include/asm
parent62d0c458f828949dd01bfe41daf3bed73ab9e288 (diff)
downloadlwn-dadf7886993c69c6838107573e250a3b3fda25e3.tar.gz
lwn-dadf7886993c69c6838107573e250a3b3fda25e3.zip
RISC-V: Add defines for SBI debug console extension
We add SBI debug console extension related defines/enum to the asm/sbi.h header. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv/include/asm')
-rw-r--r--arch/riscv/include/asm/sbi.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 5b4a1bf5f439..12dfda6bb924 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -30,6 +30,7 @@ enum sbi_ext_id {
SBI_EXT_HSM = 0x48534D,
SBI_EXT_SRST = 0x53525354,
SBI_EXT_PMU = 0x504D55,
+ SBI_EXT_DBCN = 0x4442434E,
/* Experimentals extensions must lie within this range */
SBI_EXT_EXPERIMENTAL_START = 0x08000000,
@@ -236,6 +237,12 @@ enum sbi_pmu_ctr_type {
/* Flags defined for counter stop function */
#define SBI_PMU_STOP_FLAG_RESET (1 << 0)
+enum sbi_ext_dbcn_fid {
+ SBI_EXT_DBCN_CONSOLE_WRITE = 0,
+ SBI_EXT_DBCN_CONSOLE_READ = 1,
+ SBI_EXT_DBCN_CONSOLE_WRITE_BYTE = 2,
+};
+
#define SBI_SPEC_VERSION_DEFAULT 0x1
#define SBI_SPEC_VERSION_MAJOR_SHIFT 24
#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f