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| author | Clément Léger <cleger@rivosinc.com> | 2023-11-14 09:12:48 -0500 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-12-12 15:45:09 -0800 |
| commit | eddbfa0d849fa5a315840e8c501962252b48484d (patch) | |
| tree | 80755ce71846d7fbb5363319cfca68523ac73fe8 /arch/riscv/include/asm/hwcap.h | |
| parent | c44714c35ff861d69db9c8bb4ae1347373f817f0 (diff) | |
| download | lwn-eddbfa0d849fa5a315840e8c501962252b48484d.tar.gz lwn-eddbfa0d849fa5a315840e8c501962252b48484d.zip | |
riscv: add ISA extension parsing for Zihintntl
Add parsing for Zihintntl ISA extension[1] that was ratified in commit
0dc91f5 ("Zihintntl is ratified") of riscv-isa-manual[2].
Link: https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/view [1]
Link: https://github.com/riscv/riscv-isa-manual/commit/0dc91f505e6d [2]
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Evan Green <evan@rivosinc.com>
Link: https://lore.kernel.org/r/20231114141256.126749-13-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/include/asm/hwcap.h')
| -rw-r--r-- | arch/riscv/include/asm/hwcap.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 6a6ee93a3c9a..97d106fa0f54 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -80,6 +80,7 @@ #define RISCV_ISA_EXT_ZVKT 65 #define RISCV_ISA_EXT_ZFH 66 #define RISCV_ISA_EXT_ZFHMIN 67 +#define RISCV_ISA_EXT_ZIHINTNTL 68 #define RISCV_ISA_EXT_MAX 128 #define RISCV_ISA_EXT_INVALID U32_MAX |