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| author | Paolo Bonzini <pbonzini@redhat.com> | 2023-05-05 06:11:48 -0400 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2023-05-05 06:11:48 -0400 |
| commit | d4fba4dfdcce1e23bc769591bc2e993118391b53 (patch) | |
| tree | 5cfcfecf09c481279ed2abbd75c25761b987122e /arch/riscv/include/asm/hwcap.h | |
| parent | 1a5304fecee523060f26e2778d9d8e33c0562df3 (diff) | |
| parent | 2f4d58f7635aec014428e73ef6120c4d0377c430 (diff) | |
| download | lwn-d4fba4dfdcce1e23bc769591bc2e993118391b53.tar.gz lwn-d4fba4dfdcce1e23bc769591bc2e993118391b53.zip | |
Merge tag 'kvm-riscv-6.4-1' of https://github.com/kvm-riscv/linux into HEAD
KVM/riscv changes for 6.4
- ONE_REG interface to enable/disable SBI extensions
- Zbb extension for Guest/VM
- AIA CSR virtualization
Diffstat (limited to 'arch/riscv/include/asm/hwcap.h')
| -rw-r--r-- | arch/riscv/include/asm/hwcap.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 9af793970855..e0c40a4c63d5 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -44,10 +44,18 @@ #define RISCV_ISA_EXT_ZIHINTPAUSE 32 #define RISCV_ISA_EXT_SVNAPOT 33 #define RISCV_ISA_EXT_ZICBOZ 34 +#define RISCV_ISA_EXT_SMAIA 35 +#define RISCV_ISA_EXT_SSAIA 36 #define RISCV_ISA_EXT_MAX 64 #define RISCV_ISA_EXT_NAME_LEN_MAX 32 +#ifdef CONFIG_RISCV_M_MODE +#define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA +#else +#define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA +#endif + #ifndef __ASSEMBLY__ #include <linux/jump_label.h> |