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| author | Alexandre Ghiti <alexghiti@rivosinc.com> | 2023-07-25 15:22:46 +0200 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-08-10 08:54:29 -0700 |
| commit | 7e3811521dc3934e2ecae8458676fc4a1f62bf9f (patch) | |
| tree | a804c8230adc9cd8b1dbad23a1973b1db7ee4467 /arch/riscv/include/asm/cacheflush.h | |
| parent | d566bea4a638ff0ae824df804bc08818bace41a5 (diff) | |
| download | lwn-7e3811521dc3934e2ecae8458676fc4a1f62bf9f.tar.gz lwn-7e3811521dc3934e2ecae8458676fc4a1f62bf9f.zip | |
riscv: Implement flush_cache_vmap()
The RISC-V kernel needs a sfence.vma after a page table modification: we
used to rely on the vmalloc fault handling to emit an sfence.vma, but
commit 7d3332be011e ("riscv: mm: Pre-allocate PGD entries for
vmalloc/modules area") got rid of this path for 64-bit kernels, so now we
need to explicitly emit a sfence.vma in flush_cache_vmap().
Note that we don't need to implement flush_cache_vunmap() as the generic
code should emit a flush tlb after unmapping a vmalloc region.
Fixes: 7d3332be011e ("riscv: mm: Pre-allocate PGD entries for vmalloc/modules area")
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/r/20230725132246.817726-1-alexghiti@rivosinc.com
Cc: stable@vger.kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/include/asm/cacheflush.h')
| -rw-r--r-- | arch/riscv/include/asm/cacheflush.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h index 8091b8bf4883..b93ffddf8a61 100644 --- a/arch/riscv/include/asm/cacheflush.h +++ b/arch/riscv/include/asm/cacheflush.h @@ -37,6 +37,10 @@ static inline void flush_dcache_page(struct page *page) #define flush_icache_user_page(vma, pg, addr, len) \ flush_icache_mm(vma->vm_mm, 0) +#ifdef CONFIG_64BIT +#define flush_cache_vmap(start, end) flush_tlb_kernel_range(start, end) +#endif + #ifndef CONFIG_SMP #define flush_icache_all() local_flush_icache_all() |