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| author | Liu Yu <yu.liu@freescale.com> | 2008-10-28 11:50:21 +0800 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2008-12-03 08:19:16 -0600 |
| commit | 6a800f36acd5bf06b5fe2cb27c4d0524d60c3df5 (patch) | |
| tree | fe5611ddb3a92d5609736618aed5eb8d9e65ce7a /arch/powerpc/math-emu/fmul.c | |
| parent | 033b8a333c66e0a7dc63132c1bd65175dc98bc25 (diff) | |
| download | lwn-6a800f36acd5bf06b5fe2cb27c4d0524d60c3df5.tar.gz lwn-6a800f36acd5bf06b5fe2cb27c4d0524d60c3df5.zip | |
powerpc: Add SPE/EFP math emulation for E500v1/v2 processors.
This patch add the handlers of SPE/EFP exceptions.
The code is used to emulate float point arithmetic,
when MSR(SPE) is enabled and receive EFP data interrupt or EFP round interrupt.
This patch has no conflict with or dependence on FP math-emu.
The code has been tested by TestFloat.
Now the code doesn't support SPE/EFP instructions emulation
(it won't be called when receive program interrupt),
but it could be easily added.
Signed-off-by: Liu Yu <yu.liu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/math-emu/fmul.c')
0 files changed, 0 insertions, 0 deletions