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| author | Christophe Leroy <christophe.leroy@csgroup.eu> | 2021-03-12 12:50:24 +0000 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2021-03-29 13:22:05 +1100 |
| commit | 9b6150fb8942d92e0991b9a4b02fa2e6f6b03238 (patch) | |
| tree | 3418f7c7a3e8afb9a9bb8470fa515c7f0417ff8a /arch/powerpc/kernel/head_booke.h | |
| parent | 5b1c9a0d7f3bcac591767fa1aad1323564673b26 (diff) | |
| download | lwn-9b6150fb8942d92e0991b9a4b02fa2e6f6b03238.tar.gz lwn-9b6150fb8942d92e0991b9a4b02fa2e6f6b03238.zip | |
powerpc/32: Enable instruction translation at the same time as data translation
On 40x and 8xx, kernel text is pinned.
On book3s/32, kernel text is mapped by BATs.
Enable instruction translation at the same time as data translation, it
makes things simpler.
In syscall handler, MSR_RI can also be set at the same time because
srr0/srr1 are already saved and r1 is set properly.
On booke, translation is always on, so at the end all PPC32
have translation on early. Just update msr.
Also update comment in power_save_ppc32_restore().
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/5269c7e5f5d2117358af3a89744d75a116be27b0.1615552867.git.christophe.leroy@csgroup.eu
Diffstat (limited to 'arch/powerpc/kernel/head_booke.h')
| -rw-r--r-- | arch/powerpc/kernel/head_booke.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h index 4a5f0c9b652b..f712b9bc6d62 100644 --- a/arch/powerpc/kernel/head_booke.h +++ b/arch/powerpc/kernel/head_booke.h @@ -53,6 +53,8 @@ END_BTB_FLUSH_SECTION mfspr r11, SPRN_SRR1; \ DO_KVM BOOKE_INTERRUPT_##intno SPRN_SRR1; \ andi. r11, r11, MSR_PR; /* check whether user or kernel */\ + LOAD_REG_IMMEDIATE(r11, MSR_KERNEL); \ + mtmsr r11; \ mr r11, r1; \ beq 1f; \ BOOKE_CLEAR_BTB(r11) \ @@ -192,6 +194,8 @@ ALT_FTR_SECTION_END_IFSET(CPU_FTR_EMB_HV) DO_KVM BOOKE_INTERRUPT_##intno exc_level_srr1; \ BOOKE_CLEAR_BTB(r10) \ andi. r11,r11,MSR_PR; \ + LOAD_REG_IMMEDIATE(r11, MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \ + mtmsr r11; \ mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\ lwz r11, TASK_STACK - THREAD(r11); /* this thread's kernel stack */\ addi r11,r11,EXC_LVL_FRAME_OVERHEAD; /* allocate stack frame */\ @@ -282,8 +286,6 @@ label: #define EXC_XFER_TEMPLATE(hdlr, trap, msr, tfer, ret) \ li r10,trap; \ stw r10,_TRAP(r11); \ - lis r10,msr@h; \ - ori r10,r10,msr@l; \ bl tfer; \ .long hdlr; \ .long ret |