diff options
| author | Christophe Leroy <christophe.leroy@csgroup.eu> | 2021-03-12 12:50:24 +0000 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2021-03-29 13:22:05 +1100 |
| commit | 9b6150fb8942d92e0991b9a4b02fa2e6f6b03238 (patch) | |
| tree | 3418f7c7a3e8afb9a9bb8470fa515c7f0417ff8a /arch/powerpc/kernel/head_32.h | |
| parent | 5b1c9a0d7f3bcac591767fa1aad1323564673b26 (diff) | |
| download | lwn-9b6150fb8942d92e0991b9a4b02fa2e6f6b03238.tar.gz lwn-9b6150fb8942d92e0991b9a4b02fa2e6f6b03238.zip | |
powerpc/32: Enable instruction translation at the same time as data translation
On 40x and 8xx, kernel text is pinned.
On book3s/32, kernel text is mapped by BATs.
Enable instruction translation at the same time as data translation, it
makes things simpler.
In syscall handler, MSR_RI can also be set at the same time because
srr0/srr1 are already saved and r1 is set properly.
On booke, translation is always on, so at the end all PPC32
have translation on early. Just update msr.
Also update comment in power_save_ppc32_restore().
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/5269c7e5f5d2117358af3a89744d75a116be27b0.1615552867.git.christophe.leroy@csgroup.eu
Diffstat (limited to 'arch/powerpc/kernel/head_32.h')
| -rw-r--r-- | arch/powerpc/kernel/head_32.h | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/arch/powerpc/kernel/head_32.h b/arch/powerpc/kernel/head_32.h index 910f86642eec..88b02bd91e8e 100644 --- a/arch/powerpc/kernel/head_32.h +++ b/arch/powerpc/kernel/head_32.h @@ -63,10 +63,14 @@ mtspr SPRN_DAR, r11 /* Tag DAR, to be used in DTLB Error */ .endif #endif - LOAD_REG_IMMEDIATE(r11, MSR_KERNEL & ~(MSR_IR | MSR_RI)) /* can take DTLB miss */ - mtmsr r11 - isync + LOAD_REG_IMMEDIATE(r11, MSR_KERNEL & ~MSR_RI) /* re-enable MMU */ + mtspr SPRN_SRR1, r11 + lis r11, 1f@h + ori r11, r11, 1f@l + mtspr SPRN_SRR0, r11 mfspr r11, SPRN_SPRG_SCRATCH2 + rfi +1: stw r11,GPR1(r1) stw r11,0(r1) mr r11, r1 @@ -94,7 +98,7 @@ #elif defined(CONFIG_PPC_8xx) mtspr SPRN_EID, r2 /* Set MSR_RI */ #else - li r10, MSR_KERNEL & ~MSR_IR /* can take exceptions */ + li r10, MSR_KERNEL /* can take exceptions */ mtmsr r10 /* (except for mach check in rtas) */ #endif stw r0,GPR0(r11) @@ -179,7 +183,6 @@ label: #define EXC_XFER_TEMPLATE(hdlr, trap, msr, tfer, ret) \ li r10,trap; \ stw r10,_TRAP(r11); \ - LOAD_REG_IMMEDIATE(r10, msr); \ bl tfer; \ .long hdlr; \ .long ret |