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| author | Tang Yuantian <yuantian.tang@freescale.com> | 2014-01-20 16:26:13 +0800 |
|---|---|---|
| committer | Scott Wood <scottwood@freescale.com> | 2014-03-19 16:04:23 -0500 |
| commit | 5d1a566e51d01a8bac3f56aec87bcb93395f3255 (patch) | |
| tree | ffdec58d070eab452e56a8ed619cc0d95f539d23 /arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi | |
| parent | c7e64b9ce04aa2e3fad7396d92b5cb92056d16ac (diff) | |
| download | lwn-5d1a566e51d01a8bac3f56aec87bcb93395f3255.tar.gz lwn-5d1a566e51d01a8bac3f56aec87bcb93395f3255.zip | |
powerpc/mpc85xx: Update clock nodes in device tree
The following SoCs will be affected: p2041, p3041, p4080,
p5020, p5040, b4420, b4860, t4240
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi')
| -rw-r--r-- | arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi index 7a2697d04549..22f3b14517de 100644 --- a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi +++ b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi @@ -81,6 +81,7 @@ cpu0: PowerPC,e500mc@0 { device_type = "cpu"; reg = <0>; + clocks = <&mux0>; next-level-cache = <&L2_0>; L2_0: l2-cache { next-level-cache = <&cpc>; @@ -89,6 +90,7 @@ cpu1: PowerPC,e500mc@1 { device_type = "cpu"; reg = <1>; + clocks = <&mux1>; next-level-cache = <&L2_1>; L2_1: l2-cache { next-level-cache = <&cpc>; @@ -97,6 +99,7 @@ cpu2: PowerPC,e500mc@2 { device_type = "cpu"; reg = <2>; + clocks = <&mux2>; next-level-cache = <&L2_2>; L2_2: l2-cache { next-level-cache = <&cpc>; @@ -105,6 +108,7 @@ cpu3: PowerPC,e500mc@3 { device_type = "cpu"; reg = <3>; + clocks = <&mux3>; next-level-cache = <&L2_3>; L2_3: l2-cache { next-level-cache = <&cpc>; |