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authorFlorian Fainelli <florian.fainelli@int-evry.fr>2007-03-02 22:08:01 +0100
committerRalf Baechle <ralf@linux-mips.org>2007-03-04 19:02:45 +0000
commit8b4ac6f316b493fae511921e25c72119f7b03170 (patch)
treede435cfea5bc6d6ce319da2bc3b81e4d04050294 /arch/mips
parentbaa545fddd752f46ced034bc3d95778649b67c2d (diff)
downloadlwn-8b4ac6f316b493fae511921e25c72119f7b03170.tar.gz
lwn-8b4ac6f316b493fae511921e25c72119f7b03170.zip
[MIPS] MTX1: clear PCI errors
This patch clears PCI errors after showing more debug informations. Signed-off-by: Florian Fainelli <florian.fainelli@int-evry.fr> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/pci/ops-au1000.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/mips/pci/ops-au1000.c b/arch/mips/pci/ops-au1000.c
index 8ae46481fcb7..7932dfe5eb9b 100644
--- a/arch/mips/pci/ops-au1000.c
+++ b/arch/mips/pci/ops-au1000.c
@@ -172,7 +172,11 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
error = -1;
DBG("Au1x Master Abort\n");
} else if ((status >> 28) & 0xf) {
- DBG("PCI ERR detected: status %x\n", status);
+ DBG("PCI ERR detected: device %d, status %x\n", device, ((status >> 28) & 0xf));
+
+ /* clear errors */
+ au_writel(status & 0xf000ffff, Au1500_PCI_STATCMD);
+
*data = 0xffffffff;
error = -1;
}