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authorLinus Torvalds <torvalds@linux-foundation.org>2022-05-30 11:01:50 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2022-05-30 11:01:50 -0700
commit73d15ba6ba390caed47aa8885811d1cd7b4477f3 (patch)
tree9829502e3a038c929b33cac510d764a5ddc206e0 /arch/mips
parent2d2da475ac0eebfbf40e5c5ca8c0409d62d23424 (diff)
parent7e4fd16b38923028b01d3dbadf4ca973d885c53e (diff)
downloadlwn-73d15ba6ba390caed47aa8885811d1cd7b4477f3.tar.gz
lwn-73d15ba6ba390caed47aa8885811d1cd7b4477f3.zip
Merge tag 'mips_5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS updates from Thomas Bogendoerfer: "Cleanups and fixes" * tag 'mips_5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (38 commits) MIPS: RALINK: Define pci_remap_iospace under CONFIG_PCI_DRIVERS_GENERIC MIPS: Use memblock_add_node() in early_parse_mem() under CONFIG_NUMA MIPS: Return -EINVAL if mem parameter is empty in early_parse_mem() MIPS: Kconfig: Fix indentation and add endif comment MIPS: bmips: Fix compiler warning observed on W=1 build MIPS: Rewrite `csum_tcpudp_nofold' in plain C mips: setup: use strscpy to replace strlcpy MIPS: Octeon: add SNIC10E board MIPS: Ingenic: Refresh defconfig for CU1000-Neo and CU1830-Neo. MIPS: Ingenic: Refresh device tree for Ingenic SoCs and boards. MIPS: Ingenic: Add PWM nodes for X1830. MIPS: Octeon: fix typo in comment MIPS: loongson32: Kconfig: Remove extra space MIPS: Sibyte: remove unnecessary return variable MIPS: Use NOKPROBE_SYMBOL() instead of __kprobes annotation selftests/ftrace: Save kprobe_events to test log MIPS: tools: no need to initialise statics to 0 MIPS: Loongson: Use hwmon_device_register_with_groups() to register hwmon MIPS: VR41xx: Drop redundant spinlock initialization MIPS: smp: optimization for flush_tlb_mm when exiting ...
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/Kconfig12
-rw-r--r--arch/mips/alchemy/common/dbdma.c2
-rw-r--r--arch/mips/bmips/dma.c1
-rw-r--r--arch/mips/boot/dts/brcm/bcm97358svmb.dts2
-rw-r--r--arch/mips/boot/dts/brcm/bcm97360svmb.dts2
-rw-r--r--arch/mips/boot/dts/brcm/bcm97425svmb.dts2
-rw-r--r--arch/mips/boot/dts/ingenic/cu1000-neo.dts77
-rw-r--r--arch/mips/boot/dts/ingenic/cu1830-neo.dts76
-rw-r--r--arch/mips/boot/dts/ingenic/x1000.dtsi32
-rw-r--r--arch/mips/boot/dts/ingenic/x1830.dtsi53
-rw-r--r--arch/mips/boot/dts/mscc/jaguar2_pcb110.dts10
-rw-r--r--arch/mips/boot/dts/mscc/jaguar2_pcb111.dts10
-rw-r--r--arch/mips/boot/dts/mscc/jaguar2_pcb118.dts6
-rw-r--r--arch/mips/boot/dts/mscc/ocelot.dtsi4
-rw-r--r--arch/mips/boot/dts/mscc/ocelot_pcb120.dts6
-rw-r--r--arch/mips/boot/dts/mscc/serval_common.dtsi14
-rw-r--r--arch/mips/boot/dts/ralink/gardena_smart_gateway_mt7688.dts2
-rw-r--r--arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc1.dts26
-rw-r--r--arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc2.dts30
-rw-r--r--arch/mips/boot/dts/ralink/mt7621.dtsi2
-rw-r--r--arch/mips/boot/tools/relocs.c2
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-bootmem.c2
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c5
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-helper.c6
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-pko.c2
-rw-r--r--arch/mips/cavium-octeon/octeon-irq.c2
-rw-r--r--arch/mips/cavium-octeon/octeon-usb.c2
-rw-r--r--arch/mips/configs/cu1000-neo_defconfig2
-rw-r--r--arch/mips/configs/cu1830-neo_defconfig2
-rw-r--r--arch/mips/dec/ioasic-irq.c4
-rw-r--r--arch/mips/dec/setup.c2
-rw-r--r--arch/mips/fw/arc/memory.c2
-rw-r--r--arch/mips/include/asm/checksum.h79
-rw-r--r--arch/mips/include/asm/cpu-features.h3
-rw-r--r--arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h1
-rw-r--r--arch/mips/include/asm/mach-ip30/cpu-feature-overrides.h1
-rw-r--r--arch/mips/include/asm/mach-ralink/spaces.h2
-rw-r--r--arch/mips/include/asm/octeon/cvmx-bootinfo.h2
-rw-r--r--arch/mips/jazz/irq.c2
-rw-r--r--arch/mips/kernel/cmpxchg.c2
-rw-r--r--arch/mips/kernel/cpu-probe.c2
-rw-r--r--arch/mips/kernel/idle.c2
-rw-r--r--arch/mips/kernel/kprobes.c36
-rw-r--r--arch/mips/kernel/mips-cpc.c1
-rw-r--r--arch/mips/kernel/perf_event_mipsxx.c2
-rw-r--r--arch/mips/kernel/setup.c17
-rw-r--r--arch/mips/kernel/smp.c6
-rw-r--r--arch/mips/kvm/tlb.c2
-rw-r--r--arch/mips/loongson32/Kconfig2
-rw-r--r--arch/mips/mm/fault.c6
-rw-r--r--arch/mips/net/bpf_jit_comp32.c2
-rw-r--r--arch/mips/pci/pcie-octeon.c4
-rw-r--r--arch/mips/pic32/pic32mzda/config.c2
-rw-r--r--arch/mips/sgi-ip22/ip22-reset.c11
-rw-r--r--arch/mips/sgi-ip27/ip27-xtalk.c4
-rw-r--r--arch/mips/sgi-ip30/ip30-xtalk.c4
-rw-r--r--arch/mips/sibyte/bcm1480/setup.c4
-rw-r--r--arch/mips/tools/loongson3-llsc-check.c2
-rw-r--r--arch/mips/txx9/generic/pci.c2
-rw-r--r--arch/mips/vr41xx/common/cmu.c2
60 files changed, 358 insertions, 249 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index de3b32a507d2..6e92ca97e479 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1321,11 +1321,11 @@ config CPU_LOONGSON64
select SWIOTLB
select HAVE_KVM
help
- The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
- cores implements the MIPS64R2 instruction set with many extensions,
- including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
- 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
- Loongson-2E/2F is not covered here and will be removed in future.
+ The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
+ cores implements the MIPS64R2 instruction set with many extensions,
+ including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
+ 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
+ Loongson-2E/2F is not covered here and will be removed in future.
config LOONGSON3_ENHANCEMENT
bool "New Loongson-3 CPU Enhancements"
@@ -3255,7 +3255,7 @@ menu "CPU Power Management"
if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
source "drivers/cpufreq/Kconfig"
-endif
+endif # CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
source "drivers/cpuidle/Kconfig"
diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c
index 4ca2c28878e0..5ab043000409 100644
--- a/arch/mips/alchemy/common/dbdma.c
+++ b/arch/mips/alchemy/common/dbdma.c
@@ -574,7 +574,7 @@ u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
dp++;
}
- /* Make last descrptor point to the first. */
+ /* Make last descriptor point to the first. */
dp--;
dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(ctp->chan_desc_base));
ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
diff --git a/arch/mips/bmips/dma.c b/arch/mips/bmips/dma.c
index c535f9cb75ec..33788668cbdb 100644
--- a/arch/mips/bmips/dma.c
+++ b/arch/mips/bmips/dma.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
#include <linux/types.h>
+#include <linux/dma-map-ops.h>
#include <asm/bmips.h>
#include <asm/io.h>
diff --git a/arch/mips/boot/dts/brcm/bcm97358svmb.dts b/arch/mips/boot/dts/brcm/bcm97358svmb.dts
index 522f2c40d6e6..c17fc14d4899 100644
--- a/arch/mips/boot/dts/brcm/bcm97358svmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97358svmb.dts
@@ -78,7 +78,7 @@
&qspi {
status = "okay";
- m25p80@0 {
+ flash@0 {
compatible = "m25p80";
reg = <0>;
spi-max-frequency = <40000000>;
diff --git a/arch/mips/boot/dts/brcm/bcm97360svmb.dts b/arch/mips/boot/dts/brcm/bcm97360svmb.dts
index 01f215b08dba..c9b76f41e7a6 100644
--- a/arch/mips/boot/dts/brcm/bcm97360svmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97360svmb.dts
@@ -81,7 +81,7 @@
&qspi {
status = "okay";
- m25p80@0 {
+ flash@0 {
compatible = "m25p80";
reg = <0>;
spi-max-frequency = <40000000>;
diff --git a/arch/mips/boot/dts/brcm/bcm97425svmb.dts b/arch/mips/boot/dts/brcm/bcm97425svmb.dts
index f38934934349..289a57b912ef 100644
--- a/arch/mips/boot/dts/brcm/bcm97425svmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97425svmb.dts
@@ -116,7 +116,7 @@
&qspi {
status = "okay";
- m25p80@0 {
+ flash@0 {
compatible = "m25p80";
reg = <0>;
spi-max-frequency = <40000000>;
diff --git a/arch/mips/boot/dts/ingenic/cu1000-neo.dts b/arch/mips/boot/dts/ingenic/cu1000-neo.dts
index f98cf029efc3..c89abf94e74f 100644
--- a/arch/mips/boot/dts/ingenic/cu1000-neo.dts
+++ b/arch/mips/boot/dts/ingenic/cu1000-neo.dts
@@ -31,42 +31,6 @@
};
};
- ssi: spi-gpio {
- compatible = "spi-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
- num-chipselects = <1>;
-
- mosi-gpios = <&gpd 2 GPIO_ACTIVE_HIGH>;
- miso-gpios = <&gpd 3 GPIO_ACTIVE_HIGH>;
- sck-gpios = <&gpd 0 GPIO_ACTIVE_HIGH>;
- cs-gpios = <&gpd 1 GPIO_ACTIVE_HIGH>;
-
- status = "okay";
-
- spi-max-frequency = <50000000>;
-
- sc16is752: expander@0 {
- compatible = "nxp,sc16is752";
- reg = <0>; /* CE0 */
- spi-max-frequency = <4000000>;
-
- clocks = <&exclk_sc16is752>;
-
- interrupt-parent = <&gpc>;
- interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- exclk_sc16is752: sc16is752 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <48000000>;
- };
- };
- };
-
wlan_pwrseq: msc1-pwrseq {
compatible = "mmc-pwrseq-simple";
@@ -90,7 +54,7 @@
&ost {
/* 1500 kHz for the system timer and clocksource */
- assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
+ assigned-clocks = <&ost OST_CLK_EVENT_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
assigned-clock-rates = <1500000>, <1500000>;
};
@@ -101,6 +65,39 @@
pinctrl-0 = <&pins_uart2>;
};
+&ssi {
+ status = "okay";
+
+ num-cs = <2>;
+ cs-gpios = <0>, <&gpc 20 GPIO_ACTIVE_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_ssi>;
+
+ sc16is752: expander@0 {
+ compatible = "nxp,sc16is752";
+ reg = <0>; /* CE0 */
+
+ spi-rx-bus-width = <1>;
+ spi-tx-bus-width = <1>;
+ spi-max-frequency = <4000000>;
+
+ clocks = <&exclk_sc16is752>;
+
+ interrupt-parent = <&gpc>;
+ interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ exclk_sc16is752: sc16is752 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+ };
+};
+
&i2c0 {
status = "okay";
@@ -192,6 +189,12 @@
bias-pull-up;
};
+ pins_ssi: ssi {
+ function = "ssi";
+ groups = "ssi-dt-d", "ssi-dr-d", "ssi-clk-d", "ssi-ce0-d";
+ bias-disable;
+ };
+
pins_i2c0: i2c0 {
function = "i2c0";
groups = "i2c0-data";
diff --git a/arch/mips/boot/dts/ingenic/cu1830-neo.dts b/arch/mips/boot/dts/ingenic/cu1830-neo.dts
index cfcb40edb7d9..3c7784983332 100644
--- a/arch/mips/boot/dts/ingenic/cu1830-neo.dts
+++ b/arch/mips/boot/dts/ingenic/cu1830-neo.dts
@@ -31,42 +31,6 @@
};
};
- ssi0: spi-gpio {
- compatible = "spi-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
- num-chipselects = <1>;
-
- mosi-gpios = <&gpc 12 GPIO_ACTIVE_HIGH>;
- miso-gpios = <&gpc 11 GPIO_ACTIVE_HIGH>;
- sck-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>;
- cs-gpios = <&gpc 16 GPIO_ACTIVE_HIGH>;
-
- status = "okay";
-
- spi-max-frequency = <50000000>;
-
- sc16is752: expander@0 {
- compatible = "nxp,sc16is752";
- reg = <0>; /* CE0 */
- spi-max-frequency = <4000000>;
-
- clocks = <&exclk_sc16is752>;
-
- interrupt-parent = <&gpb>;
- interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- exclk_sc16is752: sc16is752 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <48000000>;
- };
- };
- };
-
wlan_pwrseq: msc1-pwrseq {
compatible = "mmc-pwrseq-simple";
@@ -90,7 +54,7 @@
&ost {
/* 1500 kHz for the system timer and clocksource */
- assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
+ assigned-clocks = <&ost OST_CLK_EVENT_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
assigned-clock-rates = <1500000>, <1500000>;
};
@@ -101,6 +65,38 @@
pinctrl-0 = <&pins_uart1>;
};
+&ssi0 {
+ status = "okay";
+
+ num-cs = <2>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_ssi0>;
+
+ sc16is752: expander@0 {
+ compatible = "nxp,sc16is752";
+ reg = <0>; /* CE0 */
+
+ spi-rx-bus-width = <1>;
+ spi-tx-bus-width = <1>;
+ spi-max-frequency = <4000000>;
+
+ clocks = <&exclk_sc16is752>;
+
+ interrupt-parent = <&gpb>;
+ interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ exclk_sc16is752: sc16is752 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+ };
+};
+
&i2c0 {
status = "okay";
@@ -196,6 +192,12 @@
bias-pull-up;
};
+ pins_ssi0: ssi0 {
+ function = "ssi0";
+ groups = "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-ce0", "ssi0-ce1";
+ bias-disable;
+ };
+
pins_i2c0: i2c0 {
function = "i2c0";
groups = "i2c0-data";
diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi b/arch/mips/boot/dts/ingenic/x1000.dtsi
index 8bd27edef216..ecbfed49dc77 100644
--- a/arch/mips/boot/dts/ingenic/x1000.dtsi
+++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
@@ -127,6 +127,18 @@
clocks = <&tcu TCU_CLK_WDT>;
clock-names = "wdt";
};
+
+ pwm: pwm@40 {
+ compatible = "ingenic,x1000-pwm";
+ reg = <0x40 0x50>;
+
+ #pwm-cells = <3>;
+
+ clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
+ <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
+ <&tcu TCU_CLK_TIMER4>;
+ clock-names = "timer0", "timer1", "timer2", "timer3", "timer4";
+ };
};
rtc: rtc@10003000 {
@@ -246,6 +258,25 @@
status = "disabled";
};
+ ssi: spi@10043000 {
+ compatible = "ingenic,x1000-spi";
+ reg = <0x10043000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <8>;
+
+ clocks = <&cgu X1000_CLK_SSI>;
+ clock-names = "spi";
+
+ dmas = <&pdma X1000_DMA_SSI0_RX 0xffffffff>,
+ <&pdma X1000_DMA_SSI0_TX 0xffffffff>;
+ dma-names = "rx", "tx";
+
+ status = "disabled";
+ };
+
i2c0: i2c-controller@10050000 {
compatible = "ingenic,x1000-i2c";
reg = <0x10050000 0x1000>;
@@ -291,6 +322,7 @@
pdma: dma-controller@13420000 {
compatible = "ingenic,x1000-dma";
reg = <0x13420000 0x400>, <0x13421000 0x40>;
+
#dma-cells = <2>;
interrupt-parent = <&intc>;
diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi b/arch/mips/boot/dts/ingenic/x1830.dtsi
index 2595df8671c7..efd556902cfd 100644
--- a/arch/mips/boot/dts/ingenic/x1830.dtsi
+++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
@@ -120,6 +120,20 @@
clocks = <&tcu TCU_CLK_WDT>;
clock-names = "wdt";
};
+
+ pwm: pwm@40 {
+ compatible = "ingenic,x1830-pwm", "ingenic,jz4740-pwm";
+ reg = <0x40 0x80>;
+
+ #pwm-cells = <3>;
+
+ clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
+ <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
+ <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>,
+ <&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>;
+ clock-names = "timer0", "timer1", "timer2", "timer3",
+ "timer4", "timer5", "timer6", "timer7";
+ };
};
rtc: rtc@10003000 {
@@ -226,6 +240,44 @@
status = "disabled";
};
+ ssi0: spi@10043000 {
+ compatible = "ingenic,x1830-spi", "ingenic,x1000-spi";
+ reg = <0x10043000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <9>;
+
+ clocks = <&cgu X1830_CLK_SSI0>;
+ clock-names = "spi";
+
+ dmas = <&pdma X1830_DMA_SSI0_RX 0xffffffff>,
+ <&pdma X1830_DMA_SSI0_TX 0xffffffff>;
+ dma-names = "rx", "tx";
+
+ status = "disabled";
+ };
+
+ ssi1: spi@10044000 {
+ compatible = "ingenic,x1830-spi", "ingenic,x1000-spi";
+ reg = <0x10044000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <8>;
+
+ clocks = <&cgu X1830_CLK_SSI1>;
+ clock-names = "spi";
+
+ dmas = <&pdma X1830_DMA_SSI1_RX 0xffffffff>,
+ <&pdma X1830_DMA_SSI1_TX 0xffffffff>;
+ dma-names = "rx", "tx";
+
+ status = "disabled";
+ };
+
i2c0: i2c-controller@10050000 {
compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
reg = <0x10050000 0x1000>;
@@ -280,6 +332,7 @@
pdma: dma-controller@13420000 {
compatible = "ingenic,x1830-dma";
reg = <0x13420000 0x400>, <0x13421000 0x40>;
+
#dma-cells = <2>;
interrupt-parent = <&intc>;
diff --git a/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts b/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts
index d80cd6842b2a..0ea7bc5b5746 100644
--- a/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts
+++ b/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts
@@ -180,27 +180,27 @@
pins = "GPIO_49";
function = "si";
};
- i2cmux_pins_i: i2cmux-pins-i {
+ i2cmux_pins_i: i2cmux-pins {
pins = "GPIO_17", "GPIO_18", "GPIO_20", "GPIO_21";
function = "twi_scl_m";
output-low;
};
- i2cmux_0: i2cmux-0 {
+ i2cmux_0: i2cmux-0-pins {
pins = "GPIO_17";
function = "twi_scl_m";
output-high;
};
- i2cmux_1: i2cmux-1 {
+ i2cmux_1: i2cmux-1-pins {
pins = "GPIO_18";
function = "twi_scl_m";
output-high;
};
- i2cmux_2: i2cmux-2 {
+ i2cmux_2: i2cmux-2-pins {
pins = "GPIO_20";
function = "twi_scl_m";
output-high;
};
- i2cmux_3: i2cmux-3 {
+ i2cmux_3: i2cmux-3-pins {
pins = "GPIO_21";
function = "twi_scl_m";
output-high;
diff --git a/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts b/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts
index 813c5e16013c..05d8c6a96dc4 100644
--- a/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts
+++ b/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts
@@ -79,27 +79,27 @@
};
&gpio {
- i2cmux_pins_i: i2cmux-pins-i {
+ i2cmux_pins_i: i2cmux-pins {
pins = "GPIO_17", "GPIO_18";
function = "twi_scl_m";
output-low;
};
- i2cmux_0: i2cmux-0 {
+ i2cmux_0: i2cmux-0-pins {
pins = "GPIO_17";
function = "twi_scl_m";
output-high;
};
- i2cmux_1: i2cmux-1 {
+ i2cmux_1: i2cmux-1-pins {
pins = "GPIO_18";
function = "twi_scl_m";
output-high;
};
- i2cmux_2: i2cmux-2 {
+ i2cmux_2: i2cmux-2-pins {
pins = "GPIO_20";
function = "twi_scl_m";
output-high;
};
- i2cmux_3: i2cmux-3 {
+ i2cmux_3: i2cmux-3-pins {
pins = "GPIO_21";
function = "twi_scl_m";
output-high;
diff --git a/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts b/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts
index 27c644f2d17f..cf2cf591a211 100644
--- a/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts
+++ b/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts
@@ -39,17 +39,17 @@
};
&gpio {
- i2cmux_pins_i: i2cmux-pins-i {
+ i2cmux_pins_i: i2cmux-pins {
pins = "GPIO_17", "GPIO_16";
function = "twi_scl_m";
output-low;
};
- i2cmux_0: i2cmux-0 {
+ i2cmux_0: i2cmux-0-pins {
pins = "GPIO_17";
function = "twi_scl_m";
output-high;
};
- i2cmux_1: i2cmux-1 {
+ i2cmux_1: i2cmux-1-pins {
pins = "GPIO_16";
function = "twi_scl_m";
output-high;
diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi
index e51db651af13..cfc219a72bdd 100644
--- a/arch/mips/boot/dts/mscc/ocelot.dtsi
+++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
@@ -225,7 +225,7 @@
function = "uart2";
};
- miim1: miim1 {
+ miim1_pins: miim1-pins {
pins = "GPIO_14", "GPIO_15";
function = "miim";
};
@@ -261,7 +261,7 @@
reg = <0x10700c0 0x24>;
interrupts = <15>;
pinctrl-names = "default";
- pinctrl-0 = <&miim1>;
+ pinctrl-0 = <&miim1_pins>;
status = "disabled";
};
diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
index bd240690cb37..d348742c233d 100644
--- a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
+++ b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
@@ -22,12 +22,12 @@
};
&gpio {
- phy_int_pins: phy_int_pins {
+ phy_int_pins: phy-int-pins {
pins = "GPIO_4";
function = "gpio";
};
- phy_load_save_pins: phy_load_save_pins {
+ phy_load_save_pins: phy-load-save-pins {
pins = "GPIO_10";
function = "ptp2";
};
@@ -40,7 +40,7 @@
&mdio1 {
status = "okay";
pinctrl-names = "default";
- pinctrl-0 = <&miim1>, <&phy_int_pins>, <&phy_load_save_pins>;
+ pinctrl-0 = <&miim1_pins>, <&phy_int_pins>, <&phy_load_save_pins>;
phy7: ethernet-phy@0 {
reg = <0>;
diff --git a/arch/mips/boot/dts/mscc/serval_common.dtsi b/arch/mips/boot/dts/mscc/serval_common.dtsi
index 5b404836db5e..0893de420e27 100644
--- a/arch/mips/boot/dts/mscc/serval_common.dtsi
+++ b/arch/mips/boot/dts/mscc/serval_common.dtsi
@@ -82,38 +82,38 @@
pins = "GPIO_7"; /* No "default" scl for i2c0 */
function = "twi";
};
- i2cmux_pins_i: i2cmux-pins-i {
+ i2cmux_pins_i: i2cmux-pins {
pins = "GPIO_11", "GPIO_12", "GPIO_18", "GPIO_19",
"GPIO_20", "GPIO_21";
function = "twi_scl_m";
output-low;
};
- i2cmux_0: i2cmux-0 {
+ i2cmux_0: i2cmux-0-pins {
pins = "GPIO_11";
function = "twi_scl_m";
output-high;
};
- i2cmux_1: i2cmux-1 {
+ i2cmux_1: i2cmux-1-pins {
pins = "GPIO_12";
function = "twi_scl_m";
output-high;
};
- i2cmux_2: i2cmux-2 {
+ i2cmux_2: i2cmux-2-pins {
pins = "GPIO_18";
function = "twi_scl_m";
output-high;
};
- i2cmux_3: i2cmux-3 {
+ i2cmux_3: i2cmux-3-pins {
pins = "GPIO_19";
function = "twi_scl_m";
output-high;
};
- i2cmux_4: i2cmux-4 {
+ i2cmux_4: i2cmux-4-pins {
pins = "GPIO_20";
function = "twi_scl_m";
output-high;
};
- i2cmux_5: i2cmux-5 {
+ i2cmux_5: i2cmux-5-pins {
pins = "GPIO_21";
function = "twi_scl_m";
output-high;
diff --git a/arch/mips/boot/dts/ralink/gardena_smart_gateway_mt7688.dts b/arch/mips/boot/dts/ralink/gardena_smart_gateway_mt7688.dts
index 6069b33cf09f..826e91b840a3 100644
--- a/arch/mips/boot/dts/ralink/gardena_smart_gateway_mt7688.dts
+++ b/arch/mips/boot/dts/ralink/gardena_smart_gateway_mt7688.dts
@@ -129,7 +129,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinmux_spi_spi>, <&pinmux_spi_cs1_cs>;
- m25p80@0 {
+ flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
diff --git a/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc1.dts b/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc1.dts
index 5892bcf71595..37037e4f3c3b 100644
--- a/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc1.dts
+++ b/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc1.dts
@@ -60,7 +60,7 @@
&spi0 {
status = "okay";
- m25p80@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
@@ -97,20 +97,15 @@
status = "okay";
};
-&pinctrl {
- pinctrl-names = "default";
- pinctrl-0 = <&state_default>;
-
- state_default: state-default {
- gpio-pinmux {
- groups = "rgmii2", "uart3", "wdt";
- function = "gpio";
- };
- };
+&gmac1 {
+ status = "okay";
+ phy-handle = <&ethphy4>;
};
-&ethernet {
- pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;
+&mdio {
+ ethphy4: ethernet-phy@4 {
+ reg = <4>;
+ };
};
&switch0 {
@@ -119,10 +114,5 @@
status = "okay";
label = "ethblack";
};
-
- port@4 {
- status = "okay";
- label = "ethblue";
- };
};
};
diff --git a/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc2.dts b/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc2.dts
index a7fce8de6147..a6201a119a1f 100644
--- a/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc2.dts
+++ b/arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc2.dts
@@ -44,7 +44,7 @@
&spi0 {
status = "okay";
- m25p80@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
@@ -81,29 +81,15 @@
status = "okay";
};
-&pinctrl {
- pinctrl-names = "default";
- pinctrl-0 = <&state_default>;
-
- state_default: state-default {
- gpio-pinmux {
- groups = "wdt";
- function = "gpio";
- };
- };
+&gmac1 {
+ status = "okay";
+ phy-handle = <&ethphy7>;
};
-&ethernet {
- gmac1: mac@1 {
- status = "okay";
- phy-handle = <&ethphy7>;
- };
-
- mdio-bus {
- ethphy7: ethernet-phy@7 {
- reg = <7>;
- phy-mode = "rgmii-rxid";
- };
+&mdio {
+ ethphy7: ethernet-phy@7 {
+ reg = <7>;
+ phy-mode = "rgmii-rxid";
};
};
diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi
index ee2ec78c8952..ee46ace0bcc1 100644
--- a/arch/mips/boot/dts/ralink/mt7621.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7621.dtsi
@@ -342,7 +342,7 @@
phy-mode = "rgmii-rxid";
};
- mdio-bus {
+ mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/mips/boot/tools/relocs.c b/arch/mips/boot/tools/relocs.c
index 1bf53f3524b3..02fc85f3e8ff 100644
--- a/arch/mips/boot/tools/relocs.c
+++ b/arch/mips/boot/tools/relocs.c
@@ -351,7 +351,7 @@ static void read_symtabs(FILE *fp)
static void read_relocs(FILE *fp)
{
- static unsigned long base = 0;
+ static unsigned long base;
int i, j;
if (!base) {
diff --git a/arch/mips/cavium-octeon/executive/cvmx-bootmem.c b/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
index b63ad5d42cc7..306cee07ce3f 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
@@ -318,7 +318,7 @@ int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min,
}
/*
- * Determine if this is an entry that can satisify the
+ * Determine if this is an entry that can satisfy the
* request Check to make sure entry is large enough to
* satisfy request.
*/
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
index fea71a85bb29..a92632223497 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
@@ -156,8 +156,9 @@ int __cvmx_helper_xaui_enable(int interface)
xauiCtl.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface));
xauiCtl.s.lo_pwr = 0;
- /* Issuing a reset here seems to hang some CN68XX chips. */
- if (!OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1_X) &&
+ /* Issuing a reset here seems to hang some CN66XX/CN68XX chips. */
+ if (!OCTEON_IS_MODEL(OCTEON_CN66XX) &&
+ !OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1_X) &&
!OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2_X))
xauiCtl.s.reset = 1;
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper.c b/arch/mips/cavium-octeon/executive/cvmx-helper.c
index b22f664e2d29..6f49fd9be1f3 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c
@@ -61,6 +61,12 @@ int cvmx_helper_get_number_of_interfaces(void)
{
if (OCTEON_IS_MODEL(OCTEON_CN68XX))
return 9;
+ if (OCTEON_IS_MODEL(OCTEON_CN66XX)) {
+ if (OCTEON_IS_MODEL(OCTEON_CN66XX_PASS1_0))
+ return 7;
+ else
+ return 8;
+ }
if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
return 4;
if (OCTEON_IS_MODEL(OCTEON_CN7XXX))
diff --git a/arch/mips/cavium-octeon/executive/cvmx-pko.c b/arch/mips/cavium-octeon/executive/cvmx-pko.c
index ae8806e7bce2..15faca494c80 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-pko.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-pko.c
@@ -377,7 +377,7 @@ cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue,
/*
* Check to make sure all static priority
* queues are contiguous. Also catches some
- * cases of static priorites not starting at
+ * cases of static priorities not starting at
* queue 0.
*/
if (static_priority_end != -1
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index 07d7ff5a981d..6cdcbf4de763 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -1405,7 +1405,7 @@ static void octeon_irq_init_ciu2_percpu(void)
* completed.
*
* There are 9 registers and 3 IPX levels with strides 0x1000
- * and 0x200 respectivly. Use loops to clear them.
+ * and 0x200 respectively. Use loops to clear them.
*/
for (regx = 0; regx <= 0x8000; regx += 0x1000) {
for (ipx = 0; ipx <= 0x400; ipx += 0x200)
diff --git a/arch/mips/cavium-octeon/octeon-usb.c b/arch/mips/cavium-octeon/octeon-usb.c
index 4df919d26b08..5cffe1ed2447 100644
--- a/arch/mips/cavium-octeon/octeon-usb.c
+++ b/arch/mips/cavium-octeon/octeon-usb.c
@@ -419,7 +419,7 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
/* Step 5c: Enable SuperSpeed. */
uctl_ctl.s.ref_ssp_en = 1;
- /* Step 5d: Cofngiure PHYs. SKIP */
+ /* Step 5d: Configure PHYs. SKIP */
/* Step 6a & 6b: Power up PHYs. */
uctl_ctl.s.hs_power_en = 1;
diff --git a/arch/mips/configs/cu1000-neo_defconfig b/arch/mips/configs/cu1000-neo_defconfig
index 9d75f5b77d5d..5bd55eb32fe5 100644
--- a/arch/mips/configs/cu1000-neo_defconfig
+++ b/arch/mips/configs/cu1000-neo_defconfig
@@ -61,7 +61,7 @@ CONFIG_SERIAL_SC16IS7XX_SPI=y
CONFIG_I2C=y
CONFIG_I2C_JZ4780=y
CONFIG_SPI=y
-CONFIG_SPI_GPIO=y
+CONFIG_SPI_INGENIC=y
CONFIG_GPIO_SYSFS=y
CONFIG_SENSORS_ADS7828=m
CONFIG_WATCHDOG=y
diff --git a/arch/mips/configs/cu1830-neo_defconfig b/arch/mips/configs/cu1830-neo_defconfig
index 29decd0003c6..cc69688962e8 100644
--- a/arch/mips/configs/cu1830-neo_defconfig
+++ b/arch/mips/configs/cu1830-neo_defconfig
@@ -64,7 +64,7 @@ CONFIG_SERIAL_SC16IS7XX_SPI=y
CONFIG_I2C=y
CONFIG_I2C_JZ4780=y
CONFIG_SPI=y
-CONFIG_SPI_GPIO=y
+CONFIG_SPI_INGENIC=y
CONFIG_GPIO_SYSFS=y
CONFIG_SENSORS_ADS7828=m
CONFIG_WATCHDOG=y
diff --git a/arch/mips/dec/ioasic-irq.c b/arch/mips/dec/ioasic-irq.c
index 130eb67bd3c9..971f7b46759b 100644
--- a/arch/mips/dec/ioasic-irq.c
+++ b/arch/mips/dec/ioasic-irq.c
@@ -68,13 +68,13 @@ static struct irq_chip ioasic_dma_irq_type = {
* I/O ASIC implements two kinds of DMA interrupts, informational and
* error interrupts.
*
- * The formers do not stop DMA and should be cleared as soon as possible
+ * The former do not stop DMA and should be cleared as soon as possible
* so that if they retrigger before the handler has completed, usually as
* a side effect of actions taken by the handler, then they are reissued.
* These use the `handle_edge_irq' handler that clears the request right
* away.
*
- * The latters stop DMA and do not resume it until the interrupt has been
+ * The latter stop DMA and do not resume it until the interrupt has been
* cleared. This cannot be done until after a corrective action has been
* taken and this also means they will not retrigger. Therefore they use
* the `handle_fasteoi_irq' handler that only clears the request on the
diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c
index 82b00e45ce50..6c3704f51d0d 100644
--- a/arch/mips/dec/setup.c
+++ b/arch/mips/dec/setup.c
@@ -71,7 +71,7 @@ volatile u32 *ioasic_base;
EXPORT_SYMBOL(ioasic_base);
/*
- * IRQ routing and priority tables. Priorites are set as follows:
+ * IRQ routing and priority tables. Priorities are set as follows:
*
* KN01 KN230 KN02 KN02-BA KN02-CA KN03
*
diff --git a/arch/mips/fw/arc/memory.c b/arch/mips/fw/arc/memory.c
index ef5fc1ca1b5d..66188739f54d 100644
--- a/arch/mips/fw/arc/memory.c
+++ b/arch/mips/fw/arc/memory.c
@@ -32,7 +32,7 @@ static phys_addr_t prom_mem_size[MAX_PROM_MEM] __initdata;
static unsigned int nr_prom_mem __initdata;
/*
- * For ARC firmware memory functions the unit of meassuring memory is always
+ * For ARC firmware memory functions the unit of measuring memory is always
* a 4k page of memory
*/
#define ARC_PAGE_SHIFT 12
diff --git a/arch/mips/include/asm/checksum.h b/arch/mips/include/asm/checksum.h
index 1e6c1354f245..4044eaf989ac 100644
--- a/arch/mips/include/asm/checksum.h
+++ b/arch/mips/include/asm/checksum.h
@@ -128,48 +128,45 @@ static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
__u32 len, __u8 proto,
- __wsum sum)
+ __wsum isum)
{
- unsigned long tmp = (__force unsigned long)sum;
-
- __asm__(
- " .set push # csum_tcpudp_nofold\n"
- " .set noat \n"
-#ifdef CONFIG_32BIT
- " addu %0, %2 \n"
- " sltu $1, %0, %2 \n"
- " addu %0, $1 \n"
-
- " addu %0, %3 \n"
- " sltu $1, %0, %3 \n"
- " addu %0, $1 \n"
-
- " addu %0, %4 \n"
- " sltu $1, %0, %4 \n"
- " addu %0, $1 \n"
-#endif
-#ifdef CONFIG_64BIT
- " daddu %0, %2 \n"
- " daddu %0, %3 \n"
- " daddu %0, %4 \n"
- " dsll32 $1, %0, 0 \n"
- " daddu %0, $1 \n"
- " sltu $1, %0, $1 \n"
- " dsra32 %0, %0, 0 \n"
- " addu %0, $1 \n"
-#endif
- " .set pop"
- : "=r" (tmp)
- : "0" ((__force unsigned long)daddr),
- "r" ((__force unsigned long)saddr),
-#ifdef __MIPSEL__
- "r" ((proto + len) << 8),
-#else
- "r" (proto + len),
-#endif
- "r" ((__force unsigned long)sum));
-
- return (__force __wsum)tmp;
+ const unsigned int sh32 = IS_ENABLED(CONFIG_64BIT) ? 32 : 0;
+ unsigned long sum = (__force unsigned long)daddr;
+ unsigned long tmp;
+ __u32 osum;
+
+ tmp = (__force unsigned long)saddr;
+ sum += tmp;
+
+ if (IS_ENABLED(CONFIG_32BIT))
+ sum += sum < tmp;
+
+ /*
+ * We know PROTO + LEN has the sign bit clear, so cast to a signed
+ * type to avoid an extraneous zero-extension where TMP is 64-bit.
+ */
+ tmp = (__s32)(proto + len);
+ tmp <<= IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN) ? 8 : 0;
+ sum += tmp;
+ if (IS_ENABLED(CONFIG_32BIT))
+ sum += sum < tmp;
+
+ tmp = (__force unsigned long)isum;
+ sum += tmp;
+
+ if (IS_ENABLED(CONFIG_32BIT)) {
+ sum += sum < tmp;
+ osum = sum;
+ } else if (IS_ENABLED(CONFIG_64BIT)) {
+ tmp = sum << sh32;
+ sum += tmp;
+ osum = sum < tmp;
+ osum += sum >> sh32;
+ } else {
+ BUILD_BUG();
+ }
+
+ return (__force __wsum)osum;
}
#define csum_tcpudp_nofold csum_tcpudp_nofold
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index de8cb2ccb781..c0983130a44c 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -133,6 +133,9 @@
# define raw_cpu_has_fpu 0
# endif
#else
+# if cpu_has_fpu
+# error "Forcing `cpu_has_fpu' to non-zero is not supported"
+# endif
# define raw_cpu_has_fpu cpu_has_fpu
#endif
#ifndef cpu_has_32fpr
diff --git a/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
index c8385c4e8664..568fe09332eb 100644
--- a/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
@@ -25,7 +25,6 @@
#define cpu_has_4kex 1
#define cpu_has_3k_cache 0
#define cpu_has_4k_cache 1
-#define cpu_has_fpu 1
#define cpu_has_nofpuex 0
#define cpu_has_32fpr 1
#define cpu_has_counter 1
diff --git a/arch/mips/include/asm/mach-ip30/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip30/cpu-feature-overrides.h
index 8ad0c424a9af..ce4e4c6e09e2 100644
--- a/arch/mips/include/asm/mach-ip30/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ip30/cpu-feature-overrides.h
@@ -28,7 +28,6 @@
#define cpu_has_4kex 1
#define cpu_has_3k_cache 0
#define cpu_has_4k_cache 1
-#define cpu_has_fpu 1
#define cpu_has_nofpuex 0
#define cpu_has_32fpr 1
#define cpu_has_counter 1
diff --git a/arch/mips/include/asm/mach-ralink/spaces.h b/arch/mips/include/asm/mach-ralink/spaces.h
index f7af11ea2d61..a9f0570d0f04 100644
--- a/arch/mips/include/asm/mach-ralink/spaces.h
+++ b/arch/mips/include/asm/mach-ralink/spaces.h
@@ -6,7 +6,9 @@
#define PCI_IOSIZE SZ_64K
#define IO_SPACE_LIMIT (PCI_IOSIZE - 1)
+#ifdef CONFIG_PCI_DRIVERS_GENERIC
#define pci_remap_iospace pci_remap_iospace
+#endif
#include <asm/mach-generic/spaces.h>
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
index 6c61e0a63924..c1c0b3230e0a 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
@@ -253,6 +253,7 @@ enum cvmx_board_types_enum {
CVMX_BOARD_TYPE_REDWING = 43,
CVMX_BOARD_TYPE_NIC68_4 = 44,
CVMX_BOARD_TYPE_NIC10E_66 = 45,
+ CVMX_BOARD_TYPE_SNIC10E = 50,
CVMX_BOARD_TYPE_MAX,
/*
@@ -369,6 +370,7 @@ static inline const char *cvmx_board_type_to_string(enum
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_REDWING)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC68_4)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC10E_66)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_SNIC10E)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX)
/* Customer boards listed here */
diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c
index 495ba7cc56ec..264d453876aa 100644
--- a/arch/mips/jazz/irq.c
+++ b/arch/mips/jazz/irq.c
@@ -141,7 +141,7 @@ void __init plat_time_init(void)
/*
* Set clock to 100Hz.
*
- * The R4030 timer receives an input clock of 1kHz which is divieded by
+ * The R4030 timer receives an input clock of 1kHz which is divided by
* a programmable 4-bit divider. This makes it fairly inflexible.
*/
r4030_write_reg32(JAZZ_TIMER_INTERVAL, 9);
diff --git a/arch/mips/kernel/cmpxchg.c b/arch/mips/kernel/cmpxchg.c
index ac9c8cfb2ba9..e974a4954df8 100644
--- a/arch/mips/kernel/cmpxchg.c
+++ b/arch/mips/kernel/cmpxchg.c
@@ -22,7 +22,7 @@ unsigned long __xchg_small(volatile void *ptr, unsigned long val, unsigned int s
/*
* Calculate a shift & mask that correspond to the value we wish to
- * exchange within the naturally aligned 4 byte integerthat includes
+ * exchange within the naturally aligned 4 byte integer that includes
* it.
*/
shift = (unsigned long)ptr & 0x3;
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index f0ea92937546..d510f628ee03 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -156,7 +156,7 @@ static inline void check_errata(void)
/*
* Erratum "RPS May Cause Incorrect Instruction Execution"
* This code only handles VPE0, any SMP/RTOS code
- * making use of VPE1 will be responsable for that VPE.
+ * making use of VPE1 will be responsible for that VPE.
*/
if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index 146d9fa77f75..53adcc1b2ed5 100644
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -228,7 +228,7 @@ void __init check_wait(void)
break;
/*
- * Another rev is incremeting c0_count at a reduced clock
+ * Another rev is incrementing c0_count at a reduced clock
* rate while in WAIT mode. So we basically have the choice
* between using the cp0 timer as clocksource or avoiding
* the WAIT instruction. Until more details are known,
diff --git a/arch/mips/kernel/kprobes.c b/arch/mips/kernel/kprobes.c
index 6c7f3b143fdc..316b27d0d2fb 100644
--- a/arch/mips/kernel/kprobes.c
+++ b/arch/mips/kernel/kprobes.c
@@ -44,10 +44,11 @@ static const union mips_instruction breakpoint2_insn = {
DEFINE_PER_CPU(struct kprobe *, current_kprobe);
DEFINE_PER_CPU(struct kprobe_ctlblk, kprobe_ctlblk);
-static int __kprobes insn_has_delayslot(union mips_instruction insn)
+static int insn_has_delayslot(union mips_instruction insn)
{
return __insn_has_delay_slot(insn);
}
+NOKPROBE_SYMBOL(insn_has_delayslot);
/*
* insn_has_ll_or_sc function checks whether instruction is ll or sc
@@ -56,7 +57,7 @@ static int __kprobes insn_has_delayslot(union mips_instruction insn)
* instructions; cannot do much about breakpoint in the middle of
* ll/sc pair; it is upto user to avoid those places
*/
-static int __kprobes insn_has_ll_or_sc(union mips_instruction insn)
+static int insn_has_ll_or_sc(union mips_instruction insn)
{
int ret = 0;
@@ -72,8 +73,9 @@ static int __kprobes insn_has_ll_or_sc(union mips_instruction insn)
}
return ret;
}
+NOKPROBE_SYMBOL(insn_has_ll_or_sc);
-int __kprobes arch_prepare_kprobe(struct kprobe *p)
+int arch_prepare_kprobe(struct kprobe *p)
{
union mips_instruction insn;
union mips_instruction prev_insn;
@@ -132,26 +134,30 @@ int __kprobes arch_prepare_kprobe(struct kprobe *p)
out:
return ret;
}
+NOKPROBE_SYMBOL(arch_prepare_kprobe);
-void __kprobes arch_arm_kprobe(struct kprobe *p)
+void arch_arm_kprobe(struct kprobe *p)
{
*p->addr = breakpoint_insn;
flush_insn_slot(p);
}
+NOKPROBE_SYMBOL(arch_arm_kprobe);
-void __kprobes arch_disarm_kprobe(struct kprobe *p)
+void arch_disarm_kprobe(struct kprobe *p)
{
*p->addr = p->opcode;
flush_insn_slot(p);
}
+NOKPROBE_SYMBOL(arch_disarm_kprobe);
-void __kprobes arch_remove_kprobe(struct kprobe *p)
+void arch_remove_kprobe(struct kprobe *p)
{
if (p->ainsn.insn) {
free_insn_slot(p->ainsn.insn, 0);
p->ainsn.insn = NULL;
}
}
+NOKPROBE_SYMBOL(arch_remove_kprobe);
static void save_previous_kprobe(struct kprobe_ctlblk *kcb)
{
@@ -257,7 +263,7 @@ static void prepare_singlestep(struct kprobe *p, struct pt_regs *regs,
* breakpoint trap. In case of branch instructions, the target
* epc to be restored.
*/
-static void __kprobes resume_execution(struct kprobe *p,
+static void resume_execution(struct kprobe *p,
struct pt_regs *regs,
struct kprobe_ctlblk *kcb)
{
@@ -268,8 +274,9 @@ static void __kprobes resume_execution(struct kprobe *p,
regs->cp0_epc = orig_epc + 4;
}
}
+NOKPROBE_SYMBOL(resume_execution);
-static int __kprobes kprobe_handler(struct pt_regs *regs)
+static int kprobe_handler(struct pt_regs *regs)
{
struct kprobe *p;
int ret = 0;
@@ -367,6 +374,7 @@ no_kprobe:
return ret;
}
+NOKPROBE_SYMBOL(kprobe_handler);
static inline int post_kprobe_handler(struct pt_regs *regs)
{
@@ -415,7 +423,7 @@ int kprobe_fault_handler(struct pt_regs *regs, int trapnr)
/*
* Wrapper routine for handling exceptions.
*/
-int __kprobes kprobe_exceptions_notify(struct notifier_block *self,
+int kprobe_exceptions_notify(struct notifier_block *self,
unsigned long val, void *data)
{
@@ -446,6 +454,7 @@ int __kprobes kprobe_exceptions_notify(struct notifier_block *self,
}
return ret;
}
+NOKPROBE_SYMBOL(kprobe_exceptions_notify);
/*
* Function return probe trampoline:
@@ -469,7 +478,7 @@ static void __used kretprobe_trampoline_holder(void)
void __kretprobe_trampoline(void);
-void __kprobes arch_prepare_kretprobe(struct kretprobe_instance *ri,
+void arch_prepare_kretprobe(struct kretprobe_instance *ri,
struct pt_regs *regs)
{
ri->ret_addr = (kprobe_opcode_t *) regs->regs[31];
@@ -478,11 +487,12 @@ void __kprobes arch_prepare_kretprobe(struct kretprobe_instance *ri,
/* Replace the return addr with trampoline addr */
regs->regs[31] = (unsigned long)__kretprobe_trampoline;
}
+NOKPROBE_SYMBOL(arch_prepare_kretprobe);
/*
* Called when the probe at kretprobe trampoline is hit
*/
-static int __kprobes trampoline_probe_handler(struct kprobe *p,
+static int trampoline_probe_handler(struct kprobe *p,
struct pt_regs *regs)
{
instruction_pointer(regs) = __kretprobe_trampoline_handler(regs, NULL);
@@ -493,14 +503,16 @@ static int __kprobes trampoline_probe_handler(struct kprobe *p,
*/
return 1;
}
+NOKPROBE_SYMBOL(trampoline_probe_handler);
-int __kprobes arch_trampoline_kprobe(struct kprobe *p)
+int arch_trampoline_kprobe(struct kprobe *p)
{
if (p->addr == (kprobe_opcode_t *)__kretprobe_trampoline)
return 1;
return 0;
}
+NOKPROBE_SYMBOL(arch_trampoline_kprobe);
static struct kprobe trampoline_p = {
.addr = (kprobe_opcode_t *)__kretprobe_trampoline,
diff --git a/arch/mips/kernel/mips-cpc.c b/arch/mips/kernel/mips-cpc.c
index 17aff13cd7ce..3e386f7e1545 100644
--- a/arch/mips/kernel/mips-cpc.c
+++ b/arch/mips/kernel/mips-cpc.c
@@ -28,6 +28,7 @@ phys_addr_t __weak mips_cpc_default_phys_base(void)
cpc_node = of_find_compatible_node(of_root, NULL, "mti,mips-cpc");
if (cpc_node) {
err = of_address_to_resource(cpc_node, 0, &res);
+ of_node_put(cpc_node);
if (!err)
return res.start;
}
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index 1641d274fe37..c4d6b09136b1 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -329,7 +329,7 @@ static int mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc,
for (i = mipspmu.num_counters - 1; i >= 0; i--) {
/*
* Note that some MIPS perf events can be counted by both
- * even and odd counters, wheresas many other are only by
+ * even and odd counters, whereas many other are only by
* even _or_ odd counters. This introduces an issue that
* when the former kind of event takes the counter the
* latter kind of event wants to use, then the "counter
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index ef73ba1e0ec1..2ca156a5b231 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -37,6 +37,7 @@
#include <asm/cdmm.h>
#include <asm/cpu.h>
#include <asm/debug.h>
+#include <asm/mmzone.h>
#include <asm/sections.h>
#include <asm/setup.h>
#include <asm/smp-ops.h>
@@ -344,6 +345,11 @@ static int __init early_parse_mem(char *p)
{
phys_addr_t start, size;
+ if (!p) {
+ pr_err("mem parameter is empty, do nothing\n");
+ return -EINVAL;
+ }
+
/*
* If a user specifies memory size, we
* blow away any automatically generated
@@ -359,7 +365,10 @@ static int __init early_parse_mem(char *p)
if (*p == '@')
start = memparse(p + 1, &p);
- memblock_add(start, size);
+ if (IS_ENABLED(CONFIG_NUMA))
+ memblock_add_node(start, size, pa_to_nid(start), MEMBLOCK_NONE);
+ else
+ memblock_add(start, size);
return 0;
}
@@ -554,7 +563,7 @@ static void __init bootcmdline_init(void)
* unmodified.
*/
if (IS_ENABLED(CONFIG_CMDLINE_OVERRIDE)) {
- strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE);
+ strscpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE);
return;
}
@@ -566,7 +575,7 @@ static void __init bootcmdline_init(void)
* boot_command_line to undo anything early_init_dt_scan_chosen() did.
*/
if (IS_ENABLED(CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND))
- strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE);
+ strscpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE);
else
boot_command_line[0] = 0;
@@ -628,7 +637,7 @@ static void __init arch_mem_init(char **cmdline_p)
memblock_set_bottom_up(true);
bootcmdline_init();
- strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
+ strscpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
*cmdline_p = command_line;
parse_early_param();
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index 1986d1309410..1d93b85271ba 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -518,6 +518,12 @@ static inline void smp_on_each_tlb(void (*func) (void *info), void *info)
void flush_tlb_mm(struct mm_struct *mm)
{
+ if (!mm)
+ return;
+
+ if (atomic_read(&mm->mm_users) == 0)
+ return; /* happens as a result of exit_mmap() */
+
preempt_disable();
if (cpu_has_mmid) {
diff --git a/arch/mips/kvm/tlb.c b/arch/mips/kvm/tlb.c
index a3b50d5e3b25..4e91971daae1 100644
--- a/arch/mips/kvm/tlb.c
+++ b/arch/mips/kvm/tlb.c
@@ -153,7 +153,7 @@ EXPORT_SYMBOL_GPL(kvm_vz_host_tlb_inv);
* kvm_vz_guest_tlb_lookup() - Lookup a guest VZ TLB mapping.
* @vcpu: KVM VCPU pointer.
* @gpa: Guest virtual address in a TLB mapped guest segment.
- * @gpa: Ponter to output guest physical address it maps to.
+ * @gpa: Pointer to output guest physical address it maps to.
*
* Converts a guest virtual address in a guest TLB mapped segment to a guest
* physical address, by probing the guest TLB.
diff --git a/arch/mips/loongson32/Kconfig b/arch/mips/loongson32/Kconfig
index e27879b4813b..2ef9da0016df 100644
--- a/arch/mips/loongson32/Kconfig
+++ b/arch/mips/loongson32/Kconfig
@@ -46,7 +46,7 @@ menuconfig CEVT_CSRC_LS1X
If unsure, say N.
choice
- prompt "Select clockevent/clocksource"
+ prompt "Select clockevent/clocksource"
depends on CEVT_CSRC_LS1X
default TIMER_USE_PWM0
diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c
index 44f98100e84e..b08bc556d30d 100644
--- a/arch/mips/mm/fault.c
+++ b/arch/mips/mm/fault.c
@@ -35,7 +35,7 @@ int show_unhandled_signals = 1;
* and the problem, and then passes it off to one of the appropriate
* routines.
*/
-static void __kprobes __do_page_fault(struct pt_regs *regs, unsigned long write,
+static void __do_page_fault(struct pt_regs *regs, unsigned long write,
unsigned long address)
{
struct vm_area_struct * vma = NULL;
@@ -322,8 +322,9 @@ vmalloc_fault:
}
#endif
}
+NOKPROBE_SYMBOL(__do_page_fault);
-asmlinkage void __kprobes do_page_fault(struct pt_regs *regs,
+asmlinkage void do_page_fault(struct pt_regs *regs,
unsigned long write, unsigned long address)
{
enum ctx_state prev_state;
@@ -332,3 +333,4 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs,
__do_page_fault(regs, write, address);
exception_exit(prev_state);
}
+NOKPROBE_SYMBOL(do_page_fault);
diff --git a/arch/mips/net/bpf_jit_comp32.c b/arch/mips/net/bpf_jit_comp32.c
index 044b11b65bca..83c975d5cca2 100644
--- a/arch/mips/net/bpf_jit_comp32.c
+++ b/arch/mips/net/bpf_jit_comp32.c
@@ -722,7 +722,7 @@ static void emit_atomic_r32(struct jit_context *ctx,
0, JIT_RESERVED_STACK);
/*
* Argument 1: dst+off if xchg, otherwise src, passed in register a0
- * Argument 2: src if xchg, othersize dst+off, passed in register a1
+ * Argument 2: src if xchg, otherwise dst+off, passed in register a1
*/
emit(ctx, move, MIPS_R_T9, dst);
if (code == BPF_XCHG) {
diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c
index d919a0d813a1..c9edd3fb380d 100644
--- a/arch/mips/pci/pcie-octeon.c
+++ b/arch/mips/pci/pcie-octeon.c
@@ -895,7 +895,7 @@ retry:
mem_access_subid.s.nsw = 0; /* Enable Snoop for Writes. */
mem_access_subid.s.ror = 0; /* Disable Relaxed Ordering for Reads. */
mem_access_subid.s.row = 0; /* Disable Relaxed Ordering for Writes. */
- mem_access_subid.s.ba = 0; /* PCIe Adddress Bits <63:34>. */
+ mem_access_subid.s.ba = 0; /* PCIe Address Bits <63:34>. */
/*
* Setup mem access 12-15 for port 0, 16-19 for port 1,
@@ -1345,7 +1345,7 @@ static int __cvmx_pcie_rc_initialize_gen2(int pcie_port)
mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */
mem_access_subid.s.wtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
mem_access_subid.s.rtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
- /* PCIe Adddress Bits <63:34>. */
+ /* PCIe Address Bits <63:34>. */
if (OCTEON_IS_MODEL(OCTEON_CN68XX))
mem_access_subid.cn68xx.ba = 0;
else
diff --git a/arch/mips/pic32/pic32mzda/config.c b/arch/mips/pic32/pic32mzda/config.c
index 36afe1b5b9c7..f69532007717 100644
--- a/arch/mips/pic32/pic32mzda/config.c
+++ b/arch/mips/pic32/pic32mzda/config.c
@@ -111,7 +111,7 @@ void __init pic32_config_init(void)
pic32_reset_status = readl(pic32_conf_base + PIC32_RCON);
writel(-1, PIC32_CLR(pic32_conf_base + PIC32_RCON));
- /* Device Inforation */
+ /* Device Information */
pr_info("Device Id: 0x%08x, Device Ver: 0x%04x\n",
pic32_get_device_id(),
pic32_get_device_version());
diff --git a/arch/mips/sgi-ip22/ip22-reset.c b/arch/mips/sgi-ip22/ip22-reset.c
index 9028dbbb45dd..8f0861c58080 100644
--- a/arch/mips/sgi-ip22/ip22-reset.c
+++ b/arch/mips/sgi-ip22/ip22-reset.c
@@ -11,7 +11,6 @@
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/sched/signal.h>
-#include <linux/notifier.h>
#include <linux/panic_notifier.h>
#include <linux/pm.h>
#include <linux/timer.h>
@@ -41,7 +40,7 @@
static struct timer_list power_timer, blink_timer, debounce_timer;
static unsigned long blink_timer_timeout;
-#define MACHINE_PANICED 1
+#define MACHINE_PANICKED 1
#define MACHINE_SHUTTING_DOWN 2
static int machine_state;
@@ -112,7 +111,7 @@ static void debounce(struct timer_list *unused)
return;
}
- if (machine_state & MACHINE_PANICED)
+ if (machine_state & MACHINE_PANICKED)
sgimc->cpuctrl0 |= SGIMC_CCTRL0_SYSINIT;
enable_irq(SGI_PANEL_IRQ);
@@ -120,7 +119,7 @@ static void debounce(struct timer_list *unused)
static inline void power_button(void)
{
- if (machine_state & MACHINE_PANICED)
+ if (machine_state & MACHINE_PANICKED)
return;
if ((machine_state & MACHINE_SHUTTING_DOWN) ||
@@ -167,9 +166,9 @@ static irqreturn_t panel_int(int irq, void *dev_id)
static int panic_event(struct notifier_block *this, unsigned long event,
void *ptr)
{
- if (machine_state & MACHINE_PANICED)
+ if (machine_state & MACHINE_PANICKED)
return NOTIFY_DONE;
- machine_state |= MACHINE_PANICED;
+ machine_state |= MACHINE_PANICKED;
blink_timer_timeout = PANIC_FREQ;
blink_timeout(&blink_timer);
diff --git a/arch/mips/sgi-ip27/ip27-xtalk.c b/arch/mips/sgi-ip27/ip27-xtalk.c
index 000ede156bdc..e762886d1dda 100644
--- a/arch/mips/sgi-ip27/ip27-xtalk.c
+++ b/arch/mips/sgi-ip27/ip27-xtalk.c
@@ -53,6 +53,8 @@ static void bridge_platform_create(nasid_t nasid, int widget, int masterwid)
}
platform_device_add_resources(pdev, &w1_res, 1);
platform_device_add_data(pdev, wd, sizeof(*wd));
+ /* platform_device_add_data() duplicates the data */
+ kfree(wd);
platform_device_add(pdev);
bd = kzalloc(sizeof(*bd), GFP_KERNEL);
@@ -83,6 +85,8 @@ static void bridge_platform_create(nasid_t nasid, int widget, int masterwid)
bd->io_offset = offset;
platform_device_add_data(pdev, bd, sizeof(*bd));
+ /* platform_device_add_data() duplicates the data */
+ kfree(bd);
platform_device_add(pdev);
pr_info("xtalk:n%d/%x bridge widget\n", nasid, widget);
return;
diff --git a/arch/mips/sgi-ip30/ip30-xtalk.c b/arch/mips/sgi-ip30/ip30-xtalk.c
index 8a2894645529..8129524421cb 100644
--- a/arch/mips/sgi-ip30/ip30-xtalk.c
+++ b/arch/mips/sgi-ip30/ip30-xtalk.c
@@ -63,6 +63,8 @@ static void bridge_platform_create(int widget, int masterwid)
}
platform_device_add_resources(pdev, &w1_res, 1);
platform_device_add_data(pdev, wd, sizeof(*wd));
+ /* platform_device_add_data() duplicates the data */
+ kfree(wd);
platform_device_add(pdev);
bd = kzalloc(sizeof(*bd), GFP_KERNEL);
@@ -92,6 +94,8 @@ static void bridge_platform_create(int widget, int masterwid)
bd->io_offset = IP30_SWIN_BASE(widget);
platform_device_add_data(pdev, bd, sizeof(*bd));
+ /* platform_device_add_data() duplicates the data */
+ kfree(bd);
platform_device_add(pdev);
pr_info("xtalk:%x bridge widget\n", widget);
return;
diff --git a/arch/mips/sibyte/bcm1480/setup.c b/arch/mips/sibyte/bcm1480/setup.c
index 6f34b871b08e..e3e807046a9c 100644
--- a/arch/mips/sibyte/bcm1480/setup.c
+++ b/arch/mips/sibyte/bcm1480/setup.c
@@ -34,8 +34,6 @@ static char *pass_str;
static int __init setup_bcm1x80_bcm1x55(void)
{
- int ret = 0;
-
switch (soc_pass) {
case K_SYS_REVISION_BCM1480_S0:
periph_rev = 1;
@@ -64,7 +62,7 @@ static int __init setup_bcm1x80_bcm1x55(void)
break;
}
- return ret;
+ return 0;
}
/* Setup code likely to be common to all SiByte platforms */
diff --git a/arch/mips/tools/loongson3-llsc-check.c b/arch/mips/tools/loongson3-llsc-check.c
index bdbc7b4324ec..5f68a4fa8a7e 100644
--- a/arch/mips/tools/loongson3-llsc-check.c
+++ b/arch/mips/tools/loongson3-llsc-check.c
@@ -217,7 +217,7 @@ static int check_code(uint64_t pc, uint32_t *code, size_t sz)
)
/*
- * Skip the first instructionm allowing check_ll to look backwards
+ * Skip the first instruction, allowing check_ll to look backwards
* unconditionally.
*/
advance();
diff --git a/arch/mips/txx9/generic/pci.c b/arch/mips/txx9/generic/pci.c
index fb998726bd5d..e98845543b77 100644
--- a/arch/mips/txx9/generic/pci.c
+++ b/arch/mips/txx9/generic/pci.c
@@ -225,7 +225,7 @@ txx9_alloc_pci_controller(struct pci_controller *pcic,
static int __init
txx9_arch_pci_init(void)
{
- PCIBIOS_MIN_IO = 0x8000; /* reseve legacy I/O space */
+ PCIBIOS_MIN_IO = 0x8000; /* reserve legacy I/O space */
return 0;
}
arch_initcall(txx9_arch_pci_init);
diff --git a/arch/mips/vr41xx/common/cmu.c b/arch/mips/vr41xx/common/cmu.c
index b59ee5479313..e4cbe116b26d 100644
--- a/arch/mips/vr41xx/common/cmu.c
+++ b/arch/mips/vr41xx/common/cmu.c
@@ -236,8 +236,6 @@ static int __init vr41xx_cmu_init(void)
if (current_cpu_type() == CPU_VR4133)
cmuclkmsk2 = cmu_read(CMUCLKMSK2);
- spin_lock_init(&cmu_lock);
-
return 0;
}