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| author | Shinya Kuribayashi <shinya.kuribayashi@necel.com> | 2009-03-18 09:04:01 +0900 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2009-03-23 23:38:04 +0100 |
| commit | 5864810bc50de57e1b4757850d3208f69579af7f (patch) | |
| tree | 918469c22095b0734d19b31f5ad56bc43a411778 /arch/mips/mm | |
| parent | d7001198366bffce4506ba21b7b0fee2de194f73 (diff) | |
| download | lwn-5864810bc50de57e1b4757850d3208f69579af7f.tar.gz lwn-5864810bc50de57e1b4757850d3208f69579af7f.zip | |
MIPS: VR5500: Enable prefetch
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm')
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index c43f4b26a690..871e828bc62a 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -780,7 +780,7 @@ static void __cpuinit probe_pcache(void) c->dcache.ways = 2; c->dcache.waybit = 0; - c->options |= MIPS_CPU_CACHE_CDEX_P; + c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH; break; case CPU_TX49XX: |