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| author | David Daney <ddaney@caviumnetworks.com> | 2008-12-11 15:33:35 -0800 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2009-01-11 09:57:24 +0000 |
| commit | ec454d8c4fee3b2feb87e594d806c0987c5dd538 (patch) | |
| tree | 4a20bf2833a369df74fc2345f0c0aba14a50870c /arch/mips/mm/tlbex.c | |
| parent | 126336f065e5d80bd2f4c3199df8a573eb0abcf7 (diff) | |
| download | lwn-ec454d8c4fee3b2feb87e594d806c0987c5dd538.tar.gz lwn-ec454d8c4fee3b2feb87e594d806c0987c5dd538.zip | |
MIPS: Add Cavium OCTEON slot into proper tlb category.
Expand the case statement for build_tlb_write_entry so that it does
the right thing on Cavium CPU variants.
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm/tlbex.c')
| -rw-r--r-- | arch/mips/mm/tlbex.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 979cf9197282..42942038d0fd 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -317,6 +317,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_BCM3302: case CPU_BCM4710: case CPU_LOONGSON2: + case CPU_CAVIUM_OCTEON: if (m4kc_tlbp_war()) uasm_i_nop(p); tlbw(p); |